High throughput rate and low delay PHY interface circuit device of DDR5 SDRAM

Abstract

The invention belongs to the technical field of chip design, and discloses a multi-PHY (Physical Layer) interface circuit device of a DDR5SDRAM (Double Data Rate 5Synchronous Dynamic Random Access Memory), which consists of a frequency ratio conversion module, a DFI (Distributed Feedback Interface) address command and data read-write module, an initialization training calibration module, an address command sending module, a data transceiving module, a configuration module and the like. The device provided by the invention can provide multi-storage particle access capability with high data rate and low latency so as to support a standard DDR5 protocol. The optimal transmission state of a path is trained by initializing the training calibration module so as to realize low delay, and DDR5 high-data-rate transmission can be supported by high-speed parallel-serial conversion completed by the address sending and data receiving and transmitting module and the high-speed clock PLL module together. The configuration module uses a configurable register to set a data read-write module and a data transceiving module, a flexible parallel multi-storage channel structure is achieved, high throughput rate transmission is achieved, meanwhile, the frequency ratio conversion module can be configured through the configuration module, operation of three frequency ratios including 1: 1, 1: 2 and 1: 4 is achieved, and support for controllers with different DFI interface frequencies is achieved.

Description

technical field [0001] The invention belongs to the technical field of chip design, and in particular relates to a high throughput and low delay PHY interface circuit device of DDR5 SDRAM. Background technique [0002] Since the 21st century, with the rapid development of artificial intelligence and big data technology, intelligent application scenarios need to process and transmit massive amounts of data, especially servers in data centers are increasingly demanding higher speed, large capacity, and high throughput storage devices . Double-rate synchronous dynamic random access memory (DDR SDRAM) is continuously updated and iteratively developed as the main memory of the computer. Its fifth-generation DDR5 has the characteristics of high capacity, high data rate, and low latency to support servers, 5G communications, multiple cameras and Application scenarios such as automobiles. Due to the different division of labor of each manufacturer in the DDR memory system, to inte...

AI Technical Summary

Problems solved by technology

[0014] (1) The existing Xilinx IP does not use the standard DFI4.0 protocol to separate the controller part from the physical PHY, so that the controller based on the DFI standard cannot be connected to the FPGA, which is not suitable for expansion and IP integration.

[0015] (2) In most of the current scientific research work, few patents involve the implementation of the entire PHY structure design, and no specific implementation device is provided

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