Semiconductor structure and forming method thereof
A semiconductor and conductive structure technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of semiconductor structure performance to be improved, to improve electrical performance, reduce pitch, reduce contact The effect of resistance
Pending Publication Date: 2021-10-26
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0003] However, even if a self-aligned electrical contact process is used to fabricate the conductive structure on the surface of the source region or the drain region, the performance of the formed semiconductor structure still needs to be improved
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[0044] As mentioned in the background art, field effect transistors formed in the prior art still need to be improved. The following will describe in detail in conjunction with the accompanying drawings.
[0045] Please refer to figure 1 , a substrate 100 is provided, and a gate structure 102 is formed on the substrate 100, the gate structure 102 extends along a first direction Y, and the gate structure 102 includes a first gate structure 102 extending along the first direction Y. Region I and the second region II; the source-drain doped layer 103 in the substrate 100 on both sides of the gate structure 102 in the first region I; the first conductive structure 104 is formed on the source-drain doped layer 103 ; forming a second conductive structure 101 on the gate structure 102 in the second region II.
[0046] However, in this embodiment, in order to avoid a short circuit between the first conductive structure 104 and the second conductive structure 101, the second conducti...
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Abstract
The invention discloses a semiconductor structure and a forming method thereof. The method comprises: providing a substrate; forming a gate structure on the substrate; forming a source-drain doping layer in the substrate at two sides of the gate structure; forming a first conductive structure on the source-drain doping layer; forming an opening in the top of the gate structure and the first conductive structure; forming the second conductive structure electrically insulated from the first conductive structure in the opening, so that the distance between the first conductive structure and the second conductive structure can be effectively reduced, and the integration level of elements of the finally formed semiconductor structure is further improved. Besides, the insulating layer is formed in the opening, and short circuit between the first conductive structure and the second conductive structure can be effectively avoided by utilizing electrical isolation of the insulating layer, so that the electrical performance of the finally formed semiconductor structure is improved.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. For example, flash memory is used as a storage device in electronic devices such as digital cameras, notebook computers or tablet computers. Therefore, reducing the size of the flash memory unit and thereby reducing the cost of the flash memory is one of the directions of technological development. For the NOR gate electrically erasable tunnel oxide flash memory, a self-aligned electrical contact (Self-Align Contact) process can be used to manufacture the conductive structure on the surface of the source region and the drain region, so as to meet the requirements of making smaller sized flash memory requirements. ...
Claims
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IPC IPC(8): H01L29/78H01L29/423H01L21/336
CPCH01L29/66795H01L29/785H01L29/42356H01L21/76897H01L29/41791H01L23/5226H01L21/76807H01L2221/1036H01L29/45H01L23/53257H01L21/76877
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP