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Method for manufacturing semiconductor element

A technology of semiconductors and components, which is applied in the field of semiconductor manufacturing technology and can solve problems such as complicated steps

Pending Publication Date: 2021-11-05
UNITED SEMICONDUCTOR (XIAMEN) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the above-mentioned SMT manufacturing process and self-aligned metal silicide manufacturing process require multiple depositions and etchings, and the steps are relatively complicated.

Method used

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  • Method for manufacturing semiconductor element
  • Method for manufacturing semiconductor element
  • Method for manufacturing semiconductor element

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Embodiment Construction

[0066] In the following, details will be explained with reference to the accompanying drawings, the contents of which also constitute a part of the detailed description of the specification, and are shown in a specific example in which the embodiment can be practiced. The following examples are described in sufficient detail to enable those of ordinary skill in the art to practice.

[0067] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be taken as limiting, but rather the embodiments contained therein will be defined by the appended claims.

[0068] seeFigure 1 to Figure 6 , which is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Such as figure 1 As shown, a semiconductor substrate 10 is provided first, su...

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Abstract

The invention discloses a method for manufacturing a semiconductor element. The method comprises the steps: providing a semiconductor substrate having an NMOS region, a PMOS region, and a non-silicided metal region; respectively forming an NMOS transistor and a PMOS transistor in the NMOS region and the PMOS region; forming a stress memory layer to cover the NMOS region, the PMOS region and the non-silicification metal region; removing the stress memory layer from the PMOS region; transferring the stress from the stress memory layer to the N channel of the NMOS transistor; removing the stress memory layer from the NMOS region, but leaving the stress memory layer within the non-silicified metal region; carrying out a self-aligned silicification metal manufacturing process, and forming silicification metal layers in the NMOS region and the PMOS region.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing technology, in particular to a method for manufacturing semiconductor elements. Background technique [0002] It is known that Stress Memorization Technology (SMT, Stress Memorization Technology) is usually used in the semiconductor manufacturing process after the source / drain (S / D) ion implantation step to induce stress on metal oxide semiconductor field effect transistors ( MOSFET) channel area. [0003] In the traditional SMT manufacturing process, stress layer deposition and laser annealing are usually used to induce stress in the substrate, that is, the polysilicon gate located under the stress layer is recrystallized by laser annealing, thereby improving the N-channel metal oxide semiconductor field effect. The electrical properties of transistors (NMOSFET, hereinafter referred to as NMOS). The aforementioned stress layer will be removed before the subsequent self-align...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238
CPCH01L21/823814H01L21/823821H01L29/7847H01L29/665H01L29/6653H01L21/823807H01L21/823835
Inventor 胡涛施晓东欧阳锦坚谈文毅
Owner UNITED SEMICONDUCTOR (XIAMEN) CO LTD
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