106results about How to "Simple manufacturing process steps" patented technology

This invention relates to carbon nanometer tube negative electrode structure eradiation display device, wherein, the display comprises negative panel, positive panel and glass closure frame formed sealed vacuum chamber, wherein, the positive panel is grown with carbon nanometer negative electrode located on the top of the negative electrode to control the electron eradiation control grid electrode and adopts self-aligning process.

The invention discloses a dual-gate thin film transistor and a preparation method therefor, an array substrate and a display apparatus. The dual-gate thin film transistor comprises a substrate and a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a first electrode, a second electrode, a second gate and a connecting electrode which are arranged on the substrate in sequence, wherein the second gate and the first electrode and the second electrode are formed on the same layer; the first gate insulating layer comprises a first via hole for exposing a part of the first gate; and the connecting electrode is electrically connected with the second gate and electrically connected with the first gate through the first via hole. According to the dual-gate thin film transistor, the first electrode, the second electrode and the second gate are formed through a photolithography technique at the same time; by virtue of electric connection between the transparent connecting electrode and the first gate and the second gate, the dual-gate structure is realized, so that the number of film layers and masks is reduced, the production time is shortened, the production cost is lowered, capacity is effectively improved, the stability of the thin film transistor is improved, and response speed of the thin film transistor is optimized.

The invention relates to a method for separating a base plate and a semiconductor layer. The method is characterized in that a pattern silicon dioxide layer is formed between a temporary base plate and the semiconductor layer; then, the temporary base plate is separated from the pattern silicon dioxide layer by a secondary wet type etching way. The temporary base plate is removed by using the secondary wet type etching way, thereby avoiding damaging the structure of the semiconductor layer by using a the laser lift off (LLO) method. In addition, by utilizing the secondary wet type etching method, the manufacture process step is simpler, and the technical cost is decreased. On a vertical semiconductor element, the light emitting benefit of the element is increased due to the irregular surface formed by a manufacture process. In addition, by utilizing the wet type etching in the manufacture process, the batch amplification can be increased, and the cost of the manufacture process is decreased.

The invention provides a preparation method of an iron runner castable containing graphene oxide, comprising the following steps: step 1: premixing materials, and mixing raw materials and auxiliary materials evenly, wherein the raw materials contain dense corundum, white corundum, carborundum, alpha-Al2O3 micropowder, silicon dioxide micropowder, aluminate cement, ball pitch and monatomic silicon powder, and the auxiliary materials comprise a water reducer and explosion-proof fiber; step 2, adding graphene oxide solution and an antioxidant for the graphene oxide. By applying the technical scheme, the preparation method has the following effects: (1) preparation steps are simplified, and are suitable for industrial production; (2) the added graphene oxide can reduce the usage amount of common carbonaceous materials such as the ball pitch, and the production of poisonous and carcinogenic gas can be reduced when the iron runner castable is used in a high temperature environment; (3) the content of carbon in the castable can be effectively increased by the addition of the graphene oxide, the additive quantity of water and the porosity of the iron runner castable can be reduced, and the structural strength, thermal shock resistance and corrosion resistance of the iron runner castable are enhanced.

The invention provides a boron nitride reinforced multi-element heat-resistant magnesium alloy which comprises the following components in percentage by weight: 0.5-0.7% of Gd, 3.35-3.6% of Al, 1.7-1.95% of Zn, 4.0-5.0% of Si, 0.9-1.0% of Ca, 1.0-1.1% of Sr, 0.8-1.0% of Nd, 0.1-0.3% of Zr, 1-2% of Sn, 0.15-0.20% of Be, 0.7-1.0% of Mn, 0.1-0.15% of Sb, 0.5-0.8% of Cu, 1-15% of boron nitride nanotube particles and the balance of Mg, wherein the size of the boron nitride nanotube particles is below 100 microns. The invention also provides a preparation method of the alloy. The alloy has good mechanical property.

This invention relates to a manufacturing method for semiconductor elements including: carrying out first micro-image etching to form a first photoetching substratum with at least two diferent thicknesses to define a semiconductor layer of PMOS and NMOS elements by the photoetching substratum and then defining source/drain of the PMOS element by the ashed first substratum and forming a second photoetching substratum by second micro-image etching to define the grid of the PMOS and NMOS elements from the second substratum then to define a LDD of the NMOS element from the ashed second substratum.

The present invention discloses a method for manufacturing a gate oxide layer of an EEPROM (Electrically-Erasable Programmable Read-Only Memory). The method comprises the following steps: step 1, spin-coating a layer of photoresist on the surface of a silicon chip, wherein after exposing and developing, the photoresist only covers a low voltage device area and an area on which a tunneling oxide layer will form, wherein a storage device area is fully exposed except the area containing the tunneling oxide and a high pressure device area is also fully exposed; carrying out an ion implantation onthe surface of the silicon chip with the photoresist as a barrier layer of the iron implantation; and forming an ion implantation area in the silicon chip; step 2, removing the photoresist; step 3, making a high voltage oxide layer and a tunneling oxide layer grow on the surface of the silicon chip; and making a high pressure oxide layer grow in the ion implantation area formed in the step 1, wherein the thickness of the tunneling oxide layer is less than the thickness of the high voltage oxide layer. The present invention also discloses a gate oxide layer of an EEPROM manufactured by the above method. The method for manufacturing a gate oxide layer of an EEPROM has the advantages of simple processing steps, short manufacture time and low manufacture cost. Moreover, electrical characteristics of a low voltage device area can be improved.

The invention discloses a plate-type heat tube and a method for manufacturing the same. The plate-type heat tube comprises a flat hollow ring body which is provided with two opening ends, and the surface of the inner wall of the hollow ring body forms a capillary structure, wherein, a bending part is also provided next to the two opening ends and causes the hollow ring body to form airtight space, and working fluid is filled in the airtight space.

The present invention relates to a manufacturing method for the image element structure, which comprises the steps below. Firstly, the present invention provides a basal plate and form a grid on the basal plate, and then the a door dielectric layer is formed on the basal plate to cover the grid, and then a semiconductor layer is formed on the door dielectric layer, and the present invention provides a first shield cover extending partial semiconductor layer above the semiconductor layer, and the present invention uses the laser irradiation to remove partial semiconductor layer to form a channel layer, and then the present invention form a source electrode and a drain electrode on the channel layer on two sides of the grid, then the present invention form a design protecting layer to cover the channel and is uncovered from the drain electrode. Finally the present invention form a conductive layer to cover the design protecting layer and the uncovered drain electrode, and the present invention makes the conductive layer designed through the design protecting layer to form the image element electrode.

The invention discloses a graphene CVD (chemical vapor deposition) direct epitaxial growth method based on a sapphire substrate. Sapphire is used as the substrate, the sapphire substrate is reasonably pre-processed, and the growth pressure, the flow rate and the temperature are regulated, so that the graphene can directly grow on the sapphire without metals as the catalyst, and the grown graphene can be directly used to fabricate various devices without being transferred, so that the electrical characteristics and reliability of the device can be enhanced, and the complexity of fabrication of the device can be reduced. The large-area graphene material with semiconductor cleanliness is grown, the controllability of a single layer is more than 80%, and the area of a wafer is up to 8 inches.

The invention discloses a heat dissipation module, a temperature equalizing element and a manufacturing method for the temperature equalizing element. The manufacturing method for the temperature equalizing element comprises the following steps: providing a flat hollow tube body of which the inner wall surface is distributed with continuous first capillary structures; providing at least one guideelement which is placed in the flat hollow tube body and of which surface is provided with second capillary structures; connecting the first and second capillary structures to form continuous capillary structures; and filling a working fluid into the flat hollow tube body, and sealing two ends of the flat hollow tube body. In addition, the invention also provides the temperature equalizing elementand the heat dissipation module comprising the temperature equalizing element, wherein the heat dissipation module is provided with the temperature equalizing element which is used on a heating element. The manufacturing method for the temperature equalizing element comprises the steps of providing the flat hollow tube body of which inner wall surface is provided with the first capillary structures, placing the at least one guide element with a guide capillary structure into the flat hollow tube body, and making the first capillary structures and the guide capillary structure form the continuous capillary structures by using a sintering process. The manufacturing method for the temperature equalizing element can provide better flowing path for the working fluid in the temperature equalizing element.

The invention discloses a lightweight composite material train interior trim part with high-strength coatings. The train interior trim part comprises top plates, side top plates and wall plates; eachof the top plates, the side top plates and the wall plates comprises a composite sheet layer and the high-strength coating; and each composite sheet layer comprises a honeycomb material layer body, afiber material layer body and a polyurethane material layer body, wherein the fiber material layer body and the polyurethane material layer body are sequentially wrapped outside the honeycomb materiallayer body from inside to outside. Compared with the prior art, the train interior trim part has the advantages that the train interior trim part is prepared by utilizing the lightweight composite plates with the high-strength coatings, and a plurality of sheets are reasonably combined, so that the train interior trim part which is high in strength, light in weight, safe, environmentally friendly, low in cost and high in output is formed.

The invention relates to a structure of a display device and a manufacturing field of the structure of the display device, in particular to an array substrate of the display device and a manufacturing method of the array substrate of the display device. A traditional CMOS technological process is improved, the characteristic that the impedance of an ITO/Ag/ITO is low is adopted, the traditional nine photomask processes in the CMOS process is decreased to be seven photomask processes, the manufacturing process steps are simplified, yield is improved, and meanwhile the advantages of high design redundancy, low power consumption, low process and design difficulty and the like of the traditional nine photomask processes are kept.

The present invention is silent polyvinyl chloride drain pipe and its making process, and the silent polyvinyl chloride drain pipe features the extruded sound absorbing core layer between the outer layer and the inner layer. The sound absorbing core layer is produced with material including polyvinyl chloride in 100 portions, chlorinated polyvinyl chloride in 15-150 portions and barium sulfate in 50-500 portions. It has advantages of 2.7-12.9 dB lowered noise compared with common polyvinyl chloride drain pipe, rather high impact strength and tensile strength, simple production process and convenient use.

The invention discloses a Tibetan artemisia capillaris extract, a preparation method, a drug composition and an application thereof. The Tibetan artemisia capillaris is Comastoma Pedunculatum[Rogle ex D.Dou]Holub. The Tibetan artemisia capillaris extract includes at least 25% by weight of Tibetan artemisia capillaries total flavonoid glycoside. Compared with a drug composition in the prior art, the drug composition has following advantages: the Tibetan artemisia capillaris extract is high in extraction efficiency, is concentrated in effective components, is simple in steps, is low in energy consumption and less in cost, is high in effective components, is less in impurities and is convenient to control in quality, has the effects of clearing heat and removing toxin, and dispelling liver and draining bile, and can be used for treating various acute and chronic hepatitis.

The invention provides a preparation method of a P-type passivation contact crystalline silicon solar cell, and relates to the technical field of solar cells. The method comprises the following stepsof providing a P-type silicon wafer; generating a silicon oxide layer on the back surface of the silicon wafer; depositing an amorphous silicon layer on the silicon oxide layer; coating the amorphoussilicon layer with boron paste and carrying out drying to form a boron-containing barrier layer on the amorphous silicon layer; carrying out heat treatment on the silicon wafer, wherein the heat treatment comprises first heat treatment, second heat treatment and third heat treatment which are sequentially and continuously carried out; carrying out etching treatment on the silicon wafer; depositinga first passivation film on the front surface of the silicon wafer, and depositing a second passivation film on the back surface of the silicon wafer; and arranging metal electrodes on the front surface and the back surface of the silicon wafer. The three independent high-temperature treatment processes of amorphous silicon crystallization, boron diffusion and phosphorus diffusion are integratedinto one process, so that the preparation process is simplified, the yield of the battery can be improved, the production period is shortened, and the productivity is improved. Due to the fact that the high-temperature treatment process of the battery is simplified, the influence on the minority carrier service life is reduced, and the battery efficiency is improved.

The invention discloses a radio frequency SiP ceramic packaging shell and a manufacturing method thereof, the radio frequency SiP ceramic packaging shell comprises a multi-layer wiring ceramic substrate, a metal enclosure frame and a metal cover plate, the metal enclosure frame is welded on the surface of the multi-layer wiring ceramic substrate, and the metal cover plate and the metal enclosure frame are welded and fixed so as to cover the technical enclosure frame; the multilayer wiring ceramic substrate is provided with a two-stage stepped impedance matching transmission line structure witha ground coplanar waveguide-similar coaxial-strip line-similar coaxial- strip ground coplanar waveguide, the radio frequency signal transmission insertion loss can be obviously reduced while the airtightness of the packaging shell is ensured, and the light weight and miniaturization of the packaging shell are realized.

The invention provides a process for manufacturing composite ceramic covered with a photocatalyst membrane, and belongs to the technical field of ceramic. An adopted technical scheme is the process for manufacturing the composite ceramic covered with the photocatalyst membrane. The process includes preparing an aqueous solution of a peroxy-titanium system, with the concentration of the solution being 0.1-5 wt%; adding a surfactant into the aqueous solution to prepare a spraying solution; evenly coating clean and dry ceramic with the spraying solution; drying the surface; performing high-temperature calcination, with the calcination temperature being controlled to be 300-900 DEG C and the calcination time being 10-120 min; cooling the product to room temperature to obtain the composite ceramic. Beneficial effects of the process are that the process has simple and concise steps, is short in consumed time, high in efficiency and low in investment, and can be widely applied in various production lines of manufacture factories; and a product has excellent wear resistance, antibacterial performance and formaldehyde degrading performance, can efficiently clean air, can improve the environment, has beautiful gloss like organic precious stone, and is high-grade, elegant and beautiful.

The invention discloses a touch panel roll and a manufacturing method thereof. The method comprises a step of providing first and second structure rolls. A forming method of the first structure roll comprises steps of forming an opening in a first flexible substrate and extending a lead electrically connected with each electrode to the opening. A forming method of the second structure roll comprises steps of forming the lead electrically connected with each electrode and an independent lead corresponding to the lead in the first structure roll on a transparent conductive layer, wherein one ends of the leads are positioned at a position corresponding to the opening. The method also comprises a step of compressing the first structure roll and the second structure roll in a roll-to-roll mode.

This invention relates to a method for manufacturing a light doped drain region of a film transistor, which first of all forms a polysilicon layer on the base plate then forms a grating insulation layer on the polysilicon layer, after that forms a buffer and a grating on the grating insulation layer, in which, the grating is set on the buffer and exposes part of the buffer, then carries out a doping manufacture technology and forms a light doped drain region in the polysilicon layer corresponding to the lower part of the buffer exposed by the grating.

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a semiconductor substrate; a sacrificial layer on the semiconductor substrate; a functional layer located on the sacrificial layer; a pad on the functional layer; a protection layer which covers the functional layer and includes an opening through which the pad is exposed; and at least one through hole penetrating through the protection layer and the functional layer, and at least part of the sacrificial layer is exposed through the at least one through hole. In the semiconductor structure, the bonding pad is formed on the functional layer and exposed through the opening of the protection layer, so that after a part of the sacrificial layer is removed through the through hole, the protection layer does not need to be removed, the subsequent lead process can be directly carried out on the exposed bonding pad, the purpose of simplifying the manufacturing process steps is achieved, the production efficiency is improved, and the manufacturing cost is reduced.

The invention discloses environment-friendly curbstone for landscape architecture construction. The curbstone is prepared from the following raw materials in parts by weight: 15-20 parts of pulverized coal ash, 16-22 parts of clay, 8-10 parts of polypropylene fibers, 3-5 parts of epoxy resin, 10-14 parts of silicon micropowder, 1-2 parts of foamer, 18-24 parts of yellow sand, 35-48 parts of cement and 28-36 parts of water. A method for producing the environment-friendly curbstone comprises the steps: adding water into the pulverized coal ash, carrying out stirring for 1 to 2 hours, carrying out uniform mixing so as to form slurry, and maintaining the temperature of the slurry to 50 DEG C to 55 DEG C; uniformly mixing and stirring the clay, the yellow sand and the cement so as to form a dry material; adding the polypropylene fibers, the epoxy resin and the silicon micropowder into the slurry mixture in twice, then, adding the dry material into the mixture, carrying out intensive mixing, then, adding the foamer into the mixture, carrying out stirring for 20 minutes so as to form a mixed slurry material, and maintaining the temperature of the mixed slurry material to 50 DEG C to 55 DEG C so as to control the fluidity of the slurry material to 30cm; and pouring the slurry material into a mold body, carrying out standing for 60 minutes, transferring the mold body into a steam kettle, and carrying out curing for 8 hours. According to the environment-friendly curbstone for landscape architecture construction and the production method therefor, the used raw materials can achieve waste utilization, and the raw materials of the curbstone are pollution-free, so that the curbstone is relatively especially satisfactory for landscape architecture.

The invention discloses an AlN substrate-based graphene CVD direct epitaxial growth method. By adopting an II-VI family compound semiconductor AlN as a substrate, through reasonably preprocessing the AlN substrate, regulating the growth pressure, flow and temperature, the optimization of the graphene growth is realized, graphene directly grows on the AlN without using metal as a catalyst, the growing graphene is not transferred, provides a material for a AlN-graphene structure device, and can be directly used for manufacturing various devices, thus electrical properties and reliability of the devices are improved, and complexity of device manufacture is lowered. According to the AlN substrate-based graphene CVD direct epitaxial growth method, a large-area graphene material with semiconductor cleanness can be grown, the single-layer controllability exceeds 80 percent, and the area of a wafer can reach 8 inches maximally.