Method for manufacturing gate oxide layer of EEPROM and gate oxide layer manufactured thereby

Abstract

The present invention discloses a method for manufacturing a gate oxide layer of an EEPROM (Electrically-Erasable Programmable Read-Only Memory). The method comprises the following steps: step 1, spin-coating a layer of photoresist on the surface of a silicon chip, wherein after exposing and developing, the photoresist only covers a low voltage device area and an area on which a tunneling oxide layer will form, wherein a storage device area is fully exposed except the area containing the tunneling oxide and a high pressure device area is also fully exposed; carrying out an ion implantation onthe surface of the silicon chip with the photoresist as a barrier layer of the iron implantation; and forming an ion implantation area in the silicon chip; step 2, removing the photoresist; step 3, making a high voltage oxide layer and a tunneling oxide layer grow on the surface of the silicon chip; and making a high pressure oxide layer grow in the ion implantation area formed in the step 1, wherein the thickness of the tunneling oxide layer is less than the thickness of the high voltage oxide layer. The present invention also discloses a gate oxide layer of an EEPROM manufactured by the above method. The method for manufacturing a gate oxide layer of an EEPROM has the advantages of simple processing steps, short manufacture time and low manufacture cost. Moreover, electrical characteristics of a low voltage device area can be improved.

Description

technical field [0001] The invention relates to a manufacturing method of EEPROM (Electrically-Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory). Background technique [0002] see figure 1 , The existing EEPROM memory cell is composed of a selection transistor 1a and a floating gate transistor 1b. Wherein, the selection transistor 1a is usually an NMOS, and performs a gate function; the floating gate transistor 1b is usually an n-channel MOS transistor, and performs a data storage function. The selection transistor 1a and the floating gate transistor 1b share a source and drain region 11 . The floating gate transistor 1b comprises two gates 13a, 13b, with the floating gate 13a below and the control gate 13b above. [0003] In addition to the storage unit of the EEPROM, there are peripheral devices, and the peripheral devices include low-voltage devices and high-voltage devices. Typical peripheral low-voltage devices such as IO (...

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Problems solved by technology

[0015] The existing method for manufacturing the gate oxide layer of EEPROM requires two thermal oxidation growth processes plus one photolithography and etching proce

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