Array substrate of display device and manufacturing method of array substrate of display device

Abstract

The invention relates to a structure of a display device and a manufacturing field of the structure of the display device, in particular to an array substrate of the display device and a manufacturing method of the array substrate of the display device. A traditional CMOS technological process is improved, the characteristic that the impedance of an ITO/Ag/ITO is low is adopted, the traditional nine photomask processes in the CMOS process is decreased to be seven photomask processes, the manufacturing process steps are simplified, yield is improved, and meanwhile the advantages of high design redundancy, low power consumption, low process and design difficulty and the like of the traditional nine photomask processes are kept.

Description

Technical field [0001] The invention relates to the structure of a display device and the field of preparation thereof, in particular to an array substrate of a display device and a preparation method thereof. Background technique [0002] Display devices (such as Liquid Crystal Display (LCD) or Active Matrix / Organic Light Emitting Diode (AMOLED), etc.) are mainly structured by using electric field to control liquid crystal (Liquid Crystal, The light transmittance of LC) is used to display images, or the image is displayed by using current to control the light emission of organic light-emitting materials. [0003] The above-mentioned displays all need a Thin Film Transistor (TFT) array substrate to achieve voltage or current driving and control of pixels, and the TFT array substrate generally includes scan lines, signal lines, and TFT structures. . [0004] Traditionally, Low Temperature Poly-Silicon (LTPS) process is mainly used to prepare TFT array substrates to meet the high res...

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Problems solved by technology

[0015] However, in the two CMOS processes mentioned above, although the CMOS process with 8 masks uses fewer mask processes and can save a certain amount of manufacturing costs, its design redundancy is very small and the power consumption is relatively high, especially The uniformity of the threshold voltage (Vthn) of NMOS and the threshold voltage (Vthp) of PMOS is required to be high, which greatly increases the difficulty of manufacturing process and design; while the CMOS process with 9 masks can increase the redundancy of the design and reduce the power consumption. Consumption and the difficulty of manufacturing process and design, but because it has one more mask process compared with the CMOS process of 8 masks, and one mask process contains multiple process steps, which greatly increases the production cost

[0016] Chinese patent (CN102683338A) describes a low-temperature polysilicon TFT array substrate and its manufacturing method, mainly by using a gray-tone mask or a semi-transparent mask to pattern the first metal layer and the polysilicon layer, so as to achieve a single patterning process. In the process, the patterns of data lines, source electrodes, drain electrodes and polysilicon semiconductor parts are obtained at the same time; although the technical solution recorded in this patent document is to reduce the patterning process steps by optimizing the design, that is, by using a gray tone mask or a semi-transparent mask Templates are used to reduce process steps, but their compatibility with traditional process equipment is low, and new process equipment is required, which increases the cost of product preparation

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