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Wafer-level chip packaging method

A wafer-level chip and packaging method technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve problems such as chip packaging structure failure, large stress on the substrate and chip, packaging structure deformation, etc., to achieve optimization Electrical performance, improvement of stress problem, effect of reducing area

Pending Publication Date: 2021-12-03
深圳市德金元科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the above method is complex and has poor stability. Under external force or thermal shock, the packaging structure may be deformed, and large stress may be generated inside the plastic package and between the substrate and the chip, which may lead to failure of the chip packaging structure in severe cases.

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Embodiment Construction

[0064] The present invention will be further described below in conjunction with the accompanying drawings.

[0065] see as Figure 1-Figure 15 As shown, the technical solution adopted in this specific embodiment is: a wafer-level chip packaging method, including a first chip 1, a conductive pillar 11, a substrate 12, a second chip 2, a plastic package 21, a connecting pillar 3, an outer Package body 4, conductive bump 5, second pad 51, dielectric layer 52, passivation layer 521, second opening 522, pad 53, first pad 61, metal bump 62, adhesive layer 63, second One opening 64, mold 7.

[0066] Further, one or more first chips 1 are provided, and are disposed on the substrate 12 by using a semiconductor process.

[0067] Further, the substrate 12 has a conductive post 11 electrically connected to the first chip 1 , and the conductive post 11 runs through the first chip and is located above the first chip.

[0068] Further, the conductive column 11 is electrically connected t...

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Abstract

The invention discloses a wafer-level chip packaging method, and belongs to the technical field of semiconductors. The wafer-level chip packaging method comprises the steps that one or more first chips and second chips are systematically and electrically connected through conductive bumps, the chips are provided with conductive columns and metal bumps, and a plastic packaging body is provided with connecting columns for connecting, supporting and buffering deformation generated when the chip packaging structure is manufactured. And the stress problem in the plastic package body can be effectively improved. According to the invention, the advantages of the combination of wafer-level chip packaging and a system integration method are combined, the area of the packaging structure is reduced, the manufacturing cost is reduced, and the yield of the wafer-level chip packaging method is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a wafer-level chip packaging method. Background technique [0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and has become an indispensable and important tool for people today. tool. [0003] The main component of electronic equipment to achieve preset functions is the chip. With the continuous advancement of integrated circuit technology, the integration of the chip is getting higher and higher, the function of the chip is getting more and more powerful, and the size of the chip is getting smaller and smaller, so the chip needs Through packaging, a packaging structure is formed to facilitate the electrical connection of the chip with external circuits. [0004] The chip can also combine multiple logic compone...

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Application Information

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IPC IPC(8): H01L21/56H01L21/50H01L23/24
CPCH01L21/56H01L21/50H01L23/24
Inventor 黄俊凯孙晓丽何塞灵
Owner 深圳市德金元科技有限公司