Image access AXI4 bus control circuit based on FPGA and data transmission method thereof

Abstract

The invention relates to an AXI4 bus control circuit for image access based on an FPGA and a data transmission method thereof, in particular to the field of digital circuit design. The invention provides an AXI4 bus control circuit for image access based on the FPGA, wherein when video data need to be written or read, an ARM processor in the SoC can send an enable signal to enable an AXI read control state machine and an AXI write control state machine so as to start a read operation or a write operation, and can also receive an interrupt signal of the read operation or the write operation; wherein the write operation is to write continuous frame video data into a DDR3 controller adopting an AXI4 interface by adopting an AXI4 bus protocol under the operation of a write control state machine and a write state machine, and the read operation is to write the video data at the DDR3 controller end adopting the AXI4 interface into a read FIFO by utilizing an AXI read state machine and an AXI read control state machine; meanwhile, the read-write operation is controlled by double-state machines, that is, in the read or write process, the read or write operation of the AXI4 port is completed through mutual cooperation of the two state machines.

Description

technical field [0001] The present application relates to the field of digital circuits, in particular, to an FPGA-based AXI4 bus control circuit for image access and a data transmission method thereof. Background technique [0002] In recent years, with the rise of artificial intelligence and big data, the demand for processing massive data is getting higher and higher, especially in SOC chips, it is necessary to continuously improve the read and write capacity and speed of memory to meet the high performance requirements. The current SoC-based integrated circuit design method greatly shortens the design time of VLSI. In the video transmission or processing SoC circuit, because the amount of video data will occupy a large buffer space, it is necessary to store data such as DDR (DDR SDRAM) with large storage space and fast access speed to cache data. [0003] In the prior art, the SoC is usually based on an IP design mode, and uses a bus architecture to connect different mo...

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Problems solved by technology

[0006] The object of the present invention is to, aim at the above-mentioned deficiencies in the prior art, provide a kind of AXI4 bus line control circuit and data transmission method thereof based on the image access of FPGA, to solve the problem that SoC in the prior art is connected relatively between video processing modules Complex, and the internal logic is relatively complicated, it is not convenient to maintain the system, and because the connection between various related modules is relatively complicated, the data path is long

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