Manufacturing method and semiconductor structure of conductive plug
A technology of conductive plug and manufacturing method, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components and other directions, can solve the problems of poor sidewall morphology of contact holes, insufficient lithography accuracy, etc. Avoid peeling problems, solve lack of precision, optimize the effect of contact resistance
Active Publication Date: 2022-02-22
SEMICON MFG ELECTRONICS (SHAOXING) CORP +1
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Problems solved by technology
[0004] The purpose of the present invention is to provide a method for manufacturing a conductive plug and a semiconductor structure, which can improve the problems of insufficient photolithography precision and poor morphology of the sidewall of the contact hole, and then improve the reliability of the conductive plug
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[0026] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention. It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on" or...
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Abstract
The invention provides a method for manufacturing a conductive plug and a semiconductor structure. In the method for manufacturing the conductive plug, the interlayer dielectric layer is first etched to form a first opening through the interlayer dielectric layer, and then the first opening is A dielectric sidewall is formed on the sidewall of the hole, and the second opening is formed by etching the substrate with the dielectric sidewall as a mask, which can solve the problem of insufficient precision of the lithography machine in the prior art to a certain extent. The dielectric sidewall is pushed back and etched to expose the substrate top surface of the required width around the second opening, and to ensure that the sidewall of the dielectric sidewall is smooth, thereby making the side of the contact hole in the interlayer dielectric layer region The wall is smooth without delamination, thereby solving the phenomenon of insufficient or uneven thickness of the adhesion layer caused by the poor side wall morphology of the contact hole in the prior art, avoiding the peeling problem of the adhesion layer, and improving the contact hole Poor sidewall morphology leads to poor filling of conductive materials.
Description
technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for manufacturing a conductive plug and a semiconductor structure. Background technique [0002] At each technology node of semiconductor integrated circuits, electrode structures such as gate, source region, and drain region need to be drawn out through conductive plugs filled in contact holes (Contact, CT). Contact holes and conductive plugs filled in them The plug is the key structure connecting the front-end process device and the back-end metal wiring. It not only needs to have a low contact resistance, but also needs to ensure good electrical connection performance with the front-end process device. [0003] However, the conductive plugs in some existing semiconductor integrated circuits often have defects such as poor fillability due to insufficient photolithographic precision and poor contact hole sidewall morphology, resulting in low rel...
Claims
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IPC IPC(8): H01L21/768H01L21/311H01L23/528
CPCH01L21/76816H01L21/76895H01L21/31144H01L23/5283
Inventor 周旭帅露罗永华钟志鸿
Owner SEMICON MFG ELECTRONICS (SHAOXING) CORP