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Memory cell structure

A storage cell and storage electrode technology, applied in electrical components, transistors, electrical solid-state devices, etc., can solve problems such as difficulty in satisfying quality and elasticity, increasing stack capacitors, and difficult to maintain self-alignment features

Pending Publication Date: 2021-12-07
ETRON TECH INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the allowable space for the bit line to contact the drain of the access transistor is getting smaller and smaller, but self-alignment characteristics must be maintained with difficulty; Capacitance value of high dielectric constant (high-k) insulator material, otherwise the leakage current problem of the access transistor exacerbation will require increasing the capacitance value of the stack capacitor and keep increasing the height of the stack capacitor to get larger (6) because under the situation of increasingly demanding higher density / capacity and performance, there is no technical breakthrough to solve the above-mentioned difficulties, so better reliability, quality and All the ever-increasing requirements for elasticity are becoming more and more difficult to meet and so on
[0004] However, there is no technical breakthrough in the prior art to solve the above-mentioned difficulties, so how to design a new structure of the 1T1C storage unit to solve the above-mentioned difficulties has become an important issue for designers of the 1T1C storage unit

Method used

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Examples

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Embodiment Construction

[0170] Please refer to Figures 1A-1F , Figure 1A It is a flow chart of a method for manufacturing a dynamic random access memory storage cell (HCoT cell) array disclosed in an embodiment of the present invention, wherein the HCoT cell is a 1T1C memory cell, and the detailed steps of the manufacturing method are as follows:

[0171] Step 10: start;

[0172] Step 15: Based on a substrate (for example, a p-type silicon substrate), define the active area of ​​the DRAM memory cell array and form shallow trench isolation (shallow trench isolation, STI);

[0173] Step 20: forming an asymmetric spacer layer along the sidewall of the active region;

[0174] Step 25: forming an under-silicon wire (such as a bit line) between the asymmetrical spacer layers and under the horizontal surface of the substrate;

[0175] Step 30: forming the word line and gate structure of the access transistor of the DRAM memory cell array;

[0176] Step 35: defining the drain (that is, the first conduct...

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Abstract

The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery. Therefore, compared with the prior art, the memory cell structure has the advantages of more compact structure, smaller area, lower leakage current, higher capacitance value and the like.

Description

technical field [0001] The invention relates to a storage unit structure, in particular to a storage unit structure with the advantages of denser structure, smaller area, lower leakage current, higher capacitance value and the like. Background technique [0002] In the prior art, one of the most important volatile-memory integrated circuits is a Dynamic Random Access Memory (DRAM) using 1T1C memory cells. The DRAM not only provides the best cost-effective functionality as main memory and / or buffer memory for computing and communication applications, but also as a to twenty nanometers (nm) or so) shrinkage manufacturing process technology to maintain the best driving force of Moore's Law. Logic technology, which has recently continued to use embedded Static Random Access Memory (SRAM) as the driving force for its shrinking manufacturing process, claims to achieve the most advanced technology node of the manufacturing process approaching 5 nanometers. In comparison, the clai...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/02H10B12/30H10B12/34H10B12/315H10B12/0335H10B12/053H10B12/482H10B12/488H10B12/485
Inventor 卢超群
Owner ETRON TECH INC
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