Memory cell structure
A storage cell and storage electrode technology, applied in electrical components, transistors, electrical solid-state devices, etc., can solve problems such as difficulty in satisfying quality and elasticity, increasing stack capacitors, and difficult to maintain self-alignment features
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[0170] Please refer to Figures 1A-1F , Figure 1A It is a flow chart of a method for manufacturing a dynamic random access memory storage cell (HCoT cell) array disclosed in an embodiment of the present invention, wherein the HCoT cell is a 1T1C memory cell, and the detailed steps of the manufacturing method are as follows:
[0171] Step 10: start;
[0172] Step 15: Based on a substrate (for example, a p-type silicon substrate), define the active area of the DRAM memory cell array and form shallow trench isolation (shallow trench isolation, STI);
[0173] Step 20: forming an asymmetric spacer layer along the sidewall of the active region;
[0174] Step 25: forming an under-silicon wire (such as a bit line) between the asymmetrical spacer layers and under the horizontal surface of the substrate;
[0175] Step 30: forming the word line and gate structure of the access transistor of the DRAM memory cell array;
[0176] Step 35: defining the drain (that is, the first conduct...
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