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A multi-bit in-memory computing circuit

A computing circuit and multi-bit technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problem of large area and power consumption, and achieve the effect of reducing area, reducing area and power consumption, and low power consumption

Active Publication Date: 2022-02-22
中科南京智能技术研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the current design of in-memory computing, the design technology based on Static Random-Access Memory (SRAM) is mature, but the area power consumption is too large

Method used

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  • A multi-bit in-memory computing circuit
  • A multi-bit in-memory computing circuit
  • A multi-bit in-memory computing circuit

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Embodiment Construction

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0032] The purpose of the present invention is to provide a multi-bit in-memory computing circuit, which can reduce the storage array area and power consumption.

[0033] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0034] figure 1 A schematic structural diagram o...

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Abstract

The invention relates to a multi-bit in-memory computing circuit. Each memory cell in this circuit includes two resistive switching devices, which greatly reduces the area of ​​the memory array, and the power consumption of the resistive switching devices is low; the current-voltage conversion module simultaneously reads out the high-order BLL and low-order BLR two bit lines current, and add half of the high-bit current and low-bit current, and finally the current is converted into a voltage mode, and the structure of the readout circuit used is easy to read out and simplified; the column selection module makes the array share a readout circuit, reducing the overall circuit The area of ​​the readout portion in . The invention can reduce the storage array area and power consumption.

Description

technical field [0001] The invention relates to the field of circuit calculation, in particular to a multi-bit in-memory calculation circuit. Background technique [0002] Deep convolutional neural networks continue to demonstrate improvements in inference accuracy, and deep learning is moving to edge computing. This development has spurred work on low-resource machine learning algorithms and hardware to accelerate them. The most common operation in deep convolutional neural networks is multiply and accumulate (MAC), which controls power and latency. MAC operations have high regularity and parallelism, so they are very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators. Therefore, In Memory Computing (CIM) is becoming more and more attractive for accelerating deep convolutional neural networks. [0003] In the current design of in-memory computing, the design technology based...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10G06N3/08
CPCG11C7/1006G06N3/08
Inventor 乔树山黄茂森尚德龙周玉梅
Owner 中科南京智能技术研究院
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