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DBC substrate structure for balancing current of multi-chip parallel power module

A power module, multi-chip technology, applied in circuits, electrical components, electrical solid devices, etc., to improve service life, improve space utilization, and reduce warpage.

Active Publication Date: 2021-12-14
HEFEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] The technical problem to be solved by the present invention is the current sharing problem of the existing DBC substrate to cope with the parallel packaging structure of multiple SiC semiconductor chips

Method used

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  • DBC substrate structure for balancing current of multi-chip parallel power module
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  • DBC substrate structure for balancing current of multi-chip parallel power module

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Embodiment Construction

[0035] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0036] figure 1 It is a schematic diagram of the structure of the DBC substrate in the embodiment of the present invention. It can be seen from the figure that the cross-section of the DBC substrate structure is rectangular, and the order from top to bottom is: top copper layer 11, ceramic layer 12 and bottom copper layer 13. The top copper layer 11 is kept concentric with the ceramic layer 12, and each side length is 2a shorter than the corresponding side length of the ceramic layer 12, that is, a strip-shaped non-copper edge area with a width a is formed around the top copper layer 11 10.

[0037] In this embodiment, the bottom copper layer 13 has the same shape and size as the top copper layer 11 . The lower surface of the top copper layer 11 closely adheres to the upper surface of the ceramic layer 12 , and the lower surf...

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Abstract

The invention provides a DBC substrate structure for balancing current of a multi-chip parallel power module, and belongs to the technical field of module packaging. The DBC substrate structure sequentially comprises a top copper layer, a ceramic layer and a bottom copper layer from top to bottom. The SiC semiconductor chips in the top copper layer are two groups of SiC semiconductor chips which are connected in parallel and are linearly arranged on the rectangular DBC substrate in parallel, and buffer areas which are uniformly arranged are also arranged in the linear layout, so the thermal stress of the DBC substrate can be balanced, and the warping phenomenon is reduced. Meanwhile, by applying a symmetrical equidistant thought method, according to the power level of a circuit, the number of the SiC semiconductor chips connected in parallel can be expanded, the same current path and proper port positions and number can be designed, the SiC semiconductor chips mounted on the DBC substrate have balanced current distribution, and the service life of the module is prolonged.

Description

technical field [0001] The invention relates to the technical field of module packaging, and specifically provides a DBC substrate structure for balancing the current of multi-chip parallel power modules. Background technique [0002] In recent years, SiC MOSFET devices have attracted much attention in the field of power electronics because of their advantages such as high critical breakdown field strength, good thermal conductivity, small on-resistance, and higher electron saturation speed. However, in order to meet high-power applications, single-chip SiC MOSFET devices cannot meet its needs. Therefore, it is very necessary to expand the current capacity by paralleling SiC MOSFETs to meet design requirements. However, due to the dispersion of static parameters of SiC MOSFET devices and the asymmetry of the parasitic parameters of the power loop, it will lead to an imbalance in the current between parallel devices. The electrical parameters of the circuit are consistent to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/367
CPCH01L23/49838H01L23/367
Inventor 王佳宁王琛於少林刘元剑
Owner HEFEI UNIV OF TECH
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