A method and device for growing an organic semiconductor single crystal
A technology of organic semiconductor and growth direction, applied in the field of organic electronics, can solve the problems of poor crystal quality, long growth time, too small size of organic single crystal semiconductor, etc., and achieve the effect of high utilization rate of raw materials
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Embodiment 1
[0050] (1) A 20nm DNTT polycrystalline film was directly constructed on the surface of silicon dioxide modified with octadecyltrichlorosilane (OTS) by thermal evaporation.
[0051] A silicon wafer containing 300nm silicon dioxide and 500µm heavily doped silicon is selected, with a size of 1cm×1cm. With 500µm heavily doped silicon as the gate, OTS was modified by vacuum vapor method on 300nm silicon dioxide, modified at 120°C for 1 hour, and 300nm silicon dioxide and OTS were used as the dielectric layer. Then, a 20nm DNTT film is vapor-deposited on the OTS-modified silicon dioxide at an evaporation rate of 0.05Å / s. The silicon wafer is used as a loading material to download the wafer 12-3 and put it into the groove of the lower substrate 12-1. Then select only modified OTS silicon wafers containing 300nm silicon dioxide and 500µm heavily doped silicon as the upper loading chip 12-4, put into the groove of the upper substrate 12-2; put the upper substrate 12-2, the lower substr...
Embodiment 2
[0058] (1) A 20nm DNTT polycrystalline film was directly constructed on the surface of silicon dioxide modified with octadecyltrichlorosilane (OTS) by thermal evaporation.
[0059] A silicon wafer containing 300nm silicon dioxide and 500µm heavily doped silicon is selected, with a size of 1cm×1cm. With 500µm heavily doped silicon as the gate, OTS was modified by vacuum vapor method on 300nm silicon dioxide, modified at 120°C for 1 hour, and 300nm silicon dioxide and OTS were used as the dielectric layer. Then, a 20nm DNTT film is vapor-deposited on the OTS-modified silicon dioxide at an evaporation rate of 0.05Å / s. The silicon wafer is used as a loading material to download the wafer 12-3 and put it into the groove of the lower substrate 12-1. Then select only modified OTS silicon wafers containing 300nm silicon dioxide and 500µm heavily doped silicon as the upper loading chip 12-4, put into the groove of the upper substrate 12-2; put the upper substrate 12-2, the lower substr...
Embodiment 3
[0062] (2) Choose a silicon wafer containing 300nm silicon dioxide and 500µm heavily doped silicon, with a size of 1cm×1cm. Using 500µm heavily doped silicon as the gate, modify octadecyltrichlorosilane (OTS) on 300nm silicon dioxide by vacuum gas phase method, modify at 120°C for 1 hour, and use 300nm silicon dioxide and OTS as the dielectric layer.
[0063] A 20nm DPA film is evaporated on the silicon dioxide modified OTS, and the evaporation rate is 0.05Å / s. The silicon wafer is used as a loading material to download the wafer 12-3, put it into the groove of the lower substrate 12-1, and then Select the silicon wafer containing 300nm silicon dioxide and 500μm heavily doped silicon that only modifies OTS as the upper loading chip 12-4, and put it into the groove of the upper substrate 12-2; put the upper substrate 12-2, the lower substrate 12 -1 After aligning the rivet 12-5 and the rivet hole 12-6, place it on the heating table 4, adjust the position of the wire post 2 by t...
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