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A method and device for growing an organic semiconductor single crystal

A technology of organic semiconductor and growth direction, applied in the field of organic electronics, can solve the problems of poor crystal quality, long growth time, too small size of organic single crystal semiconductor, etc., and achieve the effect of high utilization rate of raw materials

Active Publication Date: 2022-04-12
TIANJIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the above methods often require more raw materials, longer growth time and special growth equipment, and the obtained organic single crystal semiconductors are too small in size or poor in crystal quality.
For the preparation of organic single crystal semiconductors, there is currently no efficient method to obtain high-quality organic semiconductor single crystals

Method used

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  • A method and device for growing an organic semiconductor single crystal
  • A method and device for growing an organic semiconductor single crystal
  • A method and device for growing an organic semiconductor single crystal

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] (1) A 20nm DNTT polycrystalline film was directly constructed on the surface of silicon dioxide modified with octadecyltrichlorosilane (OTS) by thermal evaporation.

[0051] A silicon wafer containing 300nm silicon dioxide and 500µm heavily doped silicon is selected, with a size of 1cm×1cm. With 500µm heavily doped silicon as the gate, OTS was modified by vacuum vapor method on 300nm silicon dioxide, modified at 120°C for 1 hour, and 300nm silicon dioxide and OTS were used as the dielectric layer. Then, a 20nm DNTT film is vapor-deposited on the OTS-modified silicon dioxide at an evaporation rate of 0.05Å / s. The silicon wafer is used as a loading material to download the wafer 12-3 and put it into the groove of the lower substrate 12-1. Then select only modified OTS silicon wafers containing 300nm silicon dioxide and 500µm heavily doped silicon as the upper loading chip 12-4, put into the groove of the upper substrate 12-2; put the upper substrate 12-2, the lower substr...

Embodiment 2

[0058] (1) A 20nm DNTT polycrystalline film was directly constructed on the surface of silicon dioxide modified with octadecyltrichlorosilane (OTS) by thermal evaporation.

[0059] A silicon wafer containing 300nm silicon dioxide and 500µm heavily doped silicon is selected, with a size of 1cm×1cm. With 500µm heavily doped silicon as the gate, OTS was modified by vacuum vapor method on 300nm silicon dioxide, modified at 120°C for 1 hour, and 300nm silicon dioxide and OTS were used as the dielectric layer. Then, a 20nm DNTT film is vapor-deposited on the OTS-modified silicon dioxide at an evaporation rate of 0.05Å / s. The silicon wafer is used as a loading material to download the wafer 12-3 and put it into the groove of the lower substrate 12-1. Then select only modified OTS silicon wafers containing 300nm silicon dioxide and 500µm heavily doped silicon as the upper loading chip 12-4, put into the groove of the upper substrate 12-2; put the upper substrate 12-2, the lower substr...

Embodiment 3

[0062] (2) Choose a silicon wafer containing 300nm silicon dioxide and 500µm heavily doped silicon, with a size of 1cm×1cm. Using 500µm heavily doped silicon as the gate, modify octadecyltrichlorosilane (OTS) on 300nm silicon dioxide by vacuum gas phase method, modify at 120°C for 1 hour, and use 300nm silicon dioxide and OTS as the dielectric layer.

[0063] A 20nm DPA film is evaporated on the silicon dioxide modified OTS, and the evaporation rate is 0.05Å / s. The silicon wafer is used as a loading material to download the wafer 12-3, put it into the groove of the lower substrate 12-1, and then Select the silicon wafer containing 300nm silicon dioxide and 500μm heavily doped silicon that only modifies OTS as the upper loading chip 12-4, and put it into the groove of the upper substrate 12-2; put the upper substrate 12-2, the lower substrate 12 -1 After aligning the rivet 12-5 and the rivet hole 12-6, place it on the heating table 4, adjust the position of the wire post 2 by t...

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Abstract

The invention discloses a method and a device for growing an organic semiconductor single crystal, belonging to the technical field of organic electronics. The method comprises: fixing the space confinement device of the organic semiconductor film equipped with the organic semiconductor film under pressure, then heating and cooling to obtain a large-sized organic semiconductor single crystal; the space confinement device of the organic semiconductor film is used to confine The growth direction of an organic semiconductor single crystal. The invention also provides the device used in the method. The invention uses a device that can apply different pressures and can be heated, and then controls the secondary recrystallization of the organic semiconductor thin film through the effects of temperature and space constraints, and then obtains controllable growth conditions, fast growth time and large size organic semiconductor single crystal materials.

Description

technical field [0001] The invention relates to the technical field of organic electronics, in particular to a method and device for growing an organic semiconductor single crystal. Background technique [0002] Organic semiconductor single crystals have highly ordered molecular arrangements and almost no grain boundaries inside the crystals. Compared with polycrystalline semiconductors, organic semiconductor single crystals have fewer internal defects, so they are hardly affected by grain boundary defects in the process of charge transport. Therefore, organic semiconductor single crystals are often used for the preparation of high-performance optoelectronic devices and the study of the intrinsic charge transport mechanism of materials. In addition, compared with organic semiconductor thin film materials, organic semiconductor single crystals exhibit better charge transfer ability and stability of aggregated structure. Therefore, it is the most critical technical problem to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): C30B29/54C30B23/00
CPCC30B29/54C30B23/00
Inventor 陈小松付瑶孙首港王颜鹏李立强胡文平
Owner TIANJIN UNIV