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Integrated circuit clock tree layout method, clock tree and chip

A technology of integrated circuits and layout methods, which is applied in CAD circuit design, electrical digital data processing, special data processing applications, etc., can solve problems affecting the function and performance of integrated circuits, etc. effect of error

Pending Publication Date: 2022-02-11
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the premise that the process remains unchanged, in the prior art, front-end designers can generally optimize the code and reduce the number of transistors used for combinational logic between registers to increase the frequency. However, reducing the number of transistors used for combinational logic between registers The number of transistors used to improve timing may affect the functionality and performance of integrated circuits

Method used

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  • Integrated circuit clock tree layout method, clock tree and chip
  • Integrated circuit clock tree layout method, clock tree and chip
  • Integrated circuit clock tree layout method, clock tree and chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] see figure 1 , the present embodiment is an integrated circuit clock tree layout method, which includes the following steps:

[0041] Determine the branch node of the clock layout corresponding to the clock tree, so that the first common path from the branch node to the clock signal source is the longest, and the path from the branch node to each clock region of the clock layout is the shortest; the first common path is the clock of the clock region Common path for signals.

[0042] The length of the common path from the branch node to the clock signal source depends on the physical location of each clock region and the timing check between each clock region.

[0043] Clock routing is performed based on the clock signal source, the branch node, and the clock region, so that the input end of the branch node is connected to the clock signal source, and the output end of the branch node is connected to the clock region.

[0044] Preferably, the step of determining the b...

Embodiment 2

[0048] see figure 2 , the present embodiment is an integrated circuit clock tree layout method, which includes the following steps:

[0049] Divide the clock layout into multiple clock regions according to whether the timing of the clock layout corresponding to the clock tree is violated;

[0050] Determine the branch nodes of multiple clock regions;

[0051] The principle of determining the branch node is to ensure that the first common path between multiple clock regions is the longest, and the path from the branch node to each clock region of the clock layout is the shortest. The first common path between multiple clock regions refers to the branch node A connection path to the clock signal source; wherein, the first common path is a common path of the clock signal in the clock area;

[0052] Clock area wiring: Wiring is performed between the input end of the branch node and the clock signal source, and wiring is performed between the output end and multiple clock areas....

Embodiment 3

[0059] This embodiment is an integrated circuit clock tree layout method. On the basis of Embodiment 2, it further includes dividing the clock area into multiple first-level sub-clock areas according to whether the timing of the clock area is violated;

[0060] Determining the first-level sub-branch nodes of multiple first-level sub-clock regions;

[0061] The principle for determining the first-level sub-branch nodes is to ensure that the second common path between multiple first-level sub-clock regions is the longest, and the connection path between the first-level sub-branch nodes and each sub-clock region is the shortest; among them, the second common path The path and the first common path are common paths of clock signals of each sub-clock region in the same clock region;

[0062] Level 1 sub-clock area wiring: Wiring connection between the input end of the first-level sub-branch node and the branch node, and wiring connection between the output end and multiple first-le...

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Abstract

The invention provides an integrated circuit clock tree layout method, a clock tree and a chip, and belongs to the technical field of integrated circuits. The integrated circuit clock tree layout method comprises the steps that branch nodes of a clock layout corresponding to the clock tree are determined, a first common path from the branch nodes to a clock signal source is the longest, and the path from the branch node to each clock region of the clock layout is shortest; the first common path is a common path of clock signals of the clock region; and clock wiring is performed based on a clock signal source, a branch node and the clock region, the input end of the branch node is connected with the clock signal source, and the output end of the branch node is connected with the clock region. The common paths on the clock tree are increased as much as possible from the angle of adjusting the layout of the clock tree, the influence caused by on-chip errors is reduced, and the purposes of improving the time sequence of the clock tree and improving the working frequency are achieved; and the original function and performance of the chip are not influenced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a VLSI clock tree and clock tree layout technology, in particular to an integrated circuit clock tree layout method, a clock tree and a chip. Background technique [0002] VLSI refers to an integrated circuit that combines a large number of transistors on a single chip, and its integration level is greater than that of large-scale integrated circuits. [0003] With the development of VLSI, how to increase the operating frequency under the premise of ensuring circuit performance has become a concern in the field of integrated circuits. Usually, the operating frequency depends on the size, number and operating voltage of the transistors that make up the logic gate circuit. . Transistor size and operating voltage depend on process and power requirements. On the premise that the process remains unchanged, in the prior art, front-end designers can generally optimize the co...

Claims

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Application Information

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IPC IPC(8): G06F30/3947G06F30/396G06F115/06
CPCG06F30/3947G06F30/396G06F2115/06
Inventor 白玉蓉
Owner XI AN UNIIC SEMICON CO LTD