Packaging structure and packaging method of 3D integrated circuit, and electronic device

Abstract

The invention relates to the field of semiconductor packaging, in particular to a packaging structure and a packaging method of a 3D integrated circuit and an electronic device. The packaging structure comprises a chip and component which can realize a preset function of the integrated circuit; at least two layers of substrates which are used as a carrier of the chip and component as well as substrates of each layer in the packaging structure; and at least one wiring block, wherein the wiring block an independent module, a conducting layer is electroplated or deposited in the outer side of the wiring block, connecting points are arranged at the two ends of the wiring block, the connecting points are electrically connected through metalized through holes penetrating through the whole wiring block or through holes filled with conducting materials, and the wiring block is of a closed-loop structure or an independent structure, the bonding pads or the contacts of the upper layer of substrate and the current layer of substrate are connected through the connecting points at the two ends, electrical connection between the layers of the substrates is achieved, and the connecting points serve as supporting structures between the layers of the substrates. According to the invention, the substrates are electrically connected through the wiring blocks, the production efficiency is improved, the connection size is reduced, and the wiring density is improved.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a packaging structure, packaging method and electronic device of a 3D integrated circuit. Background technique [0002] With the development of semiconductor technology, Moore's Law has approached the limit of miniaturization, and the production cost has increased exponentially. In response to the market's increasing requirements for chip volume and functions, small chips and 3D packaging are the only way for future semiconductor development. In the future, finished chips will appear in the form of combining small chips with different functions through 3D packaging. Problems existing in the prior art: [0003] 1. Moore's Law is approaching the limit; [0004] 2. The manufacturing process is getting higher and higher, the cost index is increasing, and the yield rate is decreasing. [0005] 3. The existing 3D packaging has the following problems: [0006] 1) Through-silic...

AI Technical Summary

Problems solved by technology

[0003] 1. Moore's Law is approaching the limit;

[0004] 2. The manufacturing process is getting higher and higher, the cost index is increasing, and the yield rate is decreasing

[0006] 1) Through-silicon via technology has high cost and low flexibility, and it is impossible to realize free small chip matching

[0007] 2) Through-silicon via technology is only suitable for the connection of chips and chips, and cannot realize system-level packaging

[0008] 3) TSV technology is not suitable for the connection between layers

[0009] 4) In order to realize the connection between the substrate layer and the layer, the wire bonding technology that needs to be used has technical disadvantages: the production efficiency is relatively low; the high-density connection cannot be realized; the reliability is low and the defective rate is high; The space utilization rate is low, and at the same time it is a pyramid structure. From bottom to top, the area needs to be reduced layer by layer to leave room for wiring; the size and shape of all layers from top to bottom cannot be arbitrarily defined, and the wire bonding technology cannot achieve signal impedance matching , high-speed signals cannot be integrated, and the anti-interference ability of wire bonding technology is weak, so it is inconvenient to carry out radiation protection and anti-interference reinforcement

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