Signal transmission method, equipment and device
A technology for signal transmission and signal perception, applied in transmission systems, adjustment of transmission rates, digital transmission systems, etc. It can solve the problems of inaccurate scheduling, the impact of phase errors on angle estimation performance, and the high time complexity of traversal beam scanning. The effect of reliable transmission and low latency
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Embodiment 1
[0123] Such as image 3 Shown is an application scenario of a signal transmission method provided in this embodiment.
[0124] image 3 For the convenience of description, not all the base stations, servers and terminals are shown in the example. In an actual system, there may be multiple base stations, servers and terminals coexisting, so details will not be described here.
[0125] It should be noted that, the schematic diagram of the above application scenarios is only an illustration of the applicable application scenarios of the embodiments of the present invention, and the applicable application scenarios of the embodiments of the present invention are compared with image 3 In the application scenario shown, other entities may be added, or some entities may be reduced.
[0126] Based on the above application scenarios, the embodiment of the present invention provides a signal transmission method, such as Figure 4 As shown, the method includes:
[0127] Step S401, d...
Embodiment 2
[0239] An embodiment of the present invention provides a signal transmission device, such as Figure 7 shown, including:
[0240] memory 701 , processor 702 , transceiver 703 and bus interface 704 .
[0241] The processor 702 is responsible for managing the bus architecture and general processing, and the memory 701 can store data used by the processor 702 when performing operations. The transceiver 703 is used to receive and transmit data under the control of the processor 702 .
[0242] The bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by the processor 702 and various circuits of the memory represented by the memory 701 are linked together. The bus architecture can also link together various other circuits, such as peripherals, voltage regulators, and power management circuits, etc., which are well known in the art and therefore will not be further described herein. The bus interface provides t...
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