Low-power-consumption high-resolution continuous-time Sigma-Delta modulator

Abstract

The invention discloses a continuous-time Sigma-Delta modulator with low power consumption and high resolution, the system architecture design adopts a three-order CIFF-B structure, and the power consumption and the performance are better balanced on the basis of CIFF and CIFB architectures; an operational amplifier in the integrator adopts a two-stage Class AB structure working under 1.2 V power supply voltage and a low-power-consumption limited low-frequency gain compensation scheme, so that the requirements of system resolution and linearity are met, and the power consumption is well controlled; the FIR filter is added in front of the feedback DAC, deterioration of system performance caused by clock jitter can be better restrained, the index requirement for an operational amplifier can be reduced by restraining high-frequency changes of feedback waveforms, the linearity of the system is improved, the feedback waveforms are changed into RZ waveforms from common NRZ waveforms, and the influence of ISI is avoided. In addition, extra power consumption brought by the scheme is small, and reduction of system power consumption is facilitated.

Description

Technical field [0001] The present invention belongs to the field of integrated circuit design, and specific relates to a low-power high resolution consecutive Sigma-Delta-Delta Modulator, CTSDM. Background technique [0002] Analog-to-Digital Converter, ADC can convert a continuous analog signal into a discrete digital signal, as a large component of the high-end universal chip, low power, high resolution ADC has always been simulated integration Research hotspots in the field of circuit are very wide. By using noise shaping technology and over-sampling technology, the volume of quantitative noise is transferred to the band, and then the noise filtering out of the extracted noise is obtained by the digital filter, and the Sigma-Delta ADC can obtain a high signal-to-noise distortion ratio (Signal) -to-noise-and-distortion ratio, SNDR is suitable for a scene with high resolution requirements. In addition, as the size of the electronic device tends to be miniaturized, the low power...

AI Technical Summary

Problems solved by technology

But to achieve the same signal-to-noise-distortion ratio (SNDR), a single-bit quantization modulator requires a higher loop filter order and a higher oversampling ratio

In addition, due to the limitation of low power consumption of portable devices, the jitter performance of the input clock source of the modulator is poor, which will bring huge errors to the single-bit quantization modulator. In recent years, some finite impulse response (Finite -Impulse-Response, FIR) filter cascaded feedback DAC architecture, this architecture has been proven to significantly suppress the impact of clock jitter on CTSDM conversion accuracy, but due to the use of FIR-DAC, the loop at the same sampling moment The output of the filter is different from that of the initial non-return-to-zero (NRZ) DAC, so it is necessary to add a compensation path F c (z) to make up for this difference

In addition, for DACs using NRZ pulse waveforms, the non-ideality of the rising and falling edges of the clock will cause inter-symbol interference (Inter Symbol Interference, ISI), which will affect the linearity of the feedback DAC, while using return-to-zero (Return-to -Zero, RZ) pulse feedback can solve the ISI problem, but at the same time it will increase the clock jitter sensitivity

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