Heat dissipation interconnection forming method for 3D packaging
A 3D, metal interconnection technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the 3D packaging structure heat dissipation blocked, the role of vertical heat dissipation is limited, and the interconnection density of through silicon holes. limited and other problems, to achieve the effect of increasing the vertical heat dissipation area, increasing the process cost, and reducing the layout forbidden area
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Embodiment 1
[0055] figure 1 A flow chart of a method for forming a heat dissipation interconnect structure for 3D packaging according to an embodiment of the present invention is shown; Figure 2A to Figure 2H A cross-sectional schematic diagram showing a process of forming a heat dissipation interconnect structure for 3D packaging according to an embodiment of the present invention.
[0056] In step 1, as Figure 2A As shown, a first active silicon wafer 100 is provided. The first active silicon wafer includes a wafer 101, an active region 102, a first dielectric layer 103, a metal interconnect layer 104, and a second dielectric layer 105. Active layer 102 is located on wafer 101, and active region 102 contains semiconductor devices (not shown). A metal interconnect layer 104 is located on the active region 102, and the metal interconnect layer 104 has a conductor that is electrically connected to the active region 102. The first dielectric layer 103 is configured to electrically ins...
Embodiment 2
[0073] Figure 3A to Figure 3D A schematic cross-sectional view of an active silicon wafer stacking process according to an embodiment of the present invention is shown.
[0074] This embodiment is basically the same as the first embodiment, and the difference lies in the following stacking steps of active silicon wafers:
[0075] In step 9, as Figure 3A As shown, the third active silicon wafer formed by the fourth TSV 3061 and the fifth TSV 3062 and the third metal interconnection line 308 connecting the fourth TSV 3061 and the fifth TSV 3062 will be completed The backside of 300 is thinned to expose fourth TSVs 3061, wherein the fourth TSVs have the first aperture, and the fifth TSVs have the second aperture;
[0076] In step 10, as Figure 3B As shown, a sixth dielectric layer 309 and a second pad 310 are formed on the backside of the third active silicon wafer. First, a sixth dielectric layer 309 is formed on the backside of the third active silicon wafer 300, and the...
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