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Fast convergence high-precision successive progressive analog-to-digital converter digital correction circuit and method

A fast convergence and digital correction technology, applied in the field of encoding, can solve the problems of low latency, medium and high bandwidth application scenarios, ADC can not be multiplexed, etc., and achieve the effect of high practicability, fast calibration speed, and simple configuration

Pending Publication Date: 2022-04-15
芯聚威科技(成都)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These two shortcomings make this type of ADC unable to meet some low-latency and / or medium-to-high bandwidth application scenarios. In addition, the memory effect of its internal integrator also prevents this type of ADC from being multiplexed

Method used

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  • Fast convergence high-precision successive progressive analog-to-digital converter digital correction circuit and method
  • Fast convergence high-precision successive progressive analog-to-digital converter digital correction circuit and method
  • Fast convergence high-precision successive progressive analog-to-digital converter digital correction circuit and method

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Experimental program
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Effect test

Embodiment 1

[0069] The present invention can adopt different specific designs under the same inventive concept according to different application scenarios. This embodiment is specifically described in terms of high-precision SAR ADC. Figure 1-Figure 7 As shown, the digital correction circuit of the fast convergence high-precision progressive analog-to-digital converter provided by the present invention includes a first capacitor array unit, a second capacitor array unit, a comparator unit and a SAR control logic module, and the SAR control logic modules are respectively A first switch array unit and a second switch array unit are connected, the first switch array unit connects the first capacitor array unit to Vrefp, common mode VCM and Vrefn, and the second switch array unit connects the second capacitor array unit Select one of the units to connect Vrefp, common mode VCM and Vrefn;

[0070] The negative input terminal of the comparator unit is connected to the output terminal of the s...

Embodiment 2

[0075] The present invention also provides a digital correction method, which is realized by adopting the digital correction circuit of the rapid convergence high-precision progressive analog-to-digital converter described in Embodiment 1. In particular, as one of the application scenarios of the present invention, when used for high-precision For SAR ADCs, combined with figure 1 As shown, it specifically includes the following steps:

[0076] Step STP100, input the input signal Vin into the first capacitance array unit (including the unit capacitance C through the switch Clks 1 -C N ), disconnect the switch Clks to complete the sampling;

[0077] Step STP200, receiving the result output from the comparator unit through the SAR control logic module to control the inversion of the first switch array unit to complete the conversion and quantization of the input signal Vin, and obtain the target quantization codeword;

[0078] Step STP300, close the switch Reset, and at the sa...

Embodiment 3

[0091] This embodiment is a further optimization scheme proposed on the basis of Embodiment 2. As mentioned above, if the calibration method in Embodiment 2 is used to carry out cyclic calibration, although fast convergence can be achieved, there is still room for improvement in terms of high precision, so the periodic iteration will produce the resulting periodic problem. Specifically, at every interval N+1 times, a cycle is completed. Due to the periodic operation of the capacitor array used and the digital circuit (specifically referring to all the circuit units used in the cycle), periodic disturbances will be generated on the power supply and reference voltage, which may generate periodicity in the output code word of the ADC Sexual glitches. In order to avoid this problem, in particular, on the basis of Embodiment 2, in order to avoid the glitch problem caused by periodic iterations, the method described in Embodiment 2 is optimized as follows: the current bit cell tha...

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Abstract

The invention discloses a fast convergence high-precision successive progressive analog-to-digital converter digital correction circuit and method, and the circuit comprises a first capacitor array unit, a second capacitor array unit, a comparator unit and an SAR control logic module, and the output end of the comparator unit is connected with the SAR control logic module and a digital calibration engine. According to the invention, the bypass operation is executed on the first capacitor array unit in sequence to extract the mismatch error, and the weight coefficient is obtained through an algorithm, so that the calibration purpose is achieved. The method can be widely applied to a high-precision SAR and a Piped SAR ADC, the application scene is wide, the practicability is high, the calibration speed is high, simulation part configuration is simple, additional coefficients are not increased, a background calibration algorithm can be used, and input signals are irrelevant and do not depend on the input signals.

Description

technical field [0001] The invention relates to the technical field of encoding, in particular to the technical field of high-precision analog-to-digital converter correction, and in particular to a digital correction circuit and method for a fast-converging high-precision progressive analog-to-digital converter. Background technique [0002] A high-precision analog-to-digital converter (ADC) is an essential key component in many applications such as control, monitoring, sensing, and signal acquisition. At present, there are mainly two circuit architectures for the realization of high-precision ADCs, namely, oversampling delta-sigma analog-to-digital converters and successively progressive (SAR) (including pipelined successively progressive Pipelined-SAR) analog-to-digital converters. In principle, Delta-Sigma ADC uses oversampling and noise-shaping techniques to reduce circuit noise and quantization noise within the signal bandwidth, and then the out-of-band noise can pass ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
Inventor 周雄
Owner 芯聚威科技(成都)有限公司