Fast convergence high-precision successive progressive analog-to-digital converter digital correction circuit and method
A fast convergence and digital correction technology, applied in the field of encoding, can solve the problems of low latency, medium and high bandwidth application scenarios, ADC can not be multiplexed, etc., and achieve the effect of high practicability, fast calibration speed, and simple configuration
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Embodiment 1
[0069] The present invention can adopt different specific designs under the same inventive concept according to different application scenarios. This embodiment is specifically described in terms of high-precision SAR ADC. Figure 1-Figure 7 As shown, the digital correction circuit of the fast convergence high-precision progressive analog-to-digital converter provided by the present invention includes a first capacitor array unit, a second capacitor array unit, a comparator unit and a SAR control logic module, and the SAR control logic modules are respectively A first switch array unit and a second switch array unit are connected, the first switch array unit connects the first capacitor array unit to Vrefp, common mode VCM and Vrefn, and the second switch array unit connects the second capacitor array unit Select one of the units to connect Vrefp, common mode VCM and Vrefn;
[0070] The negative input terminal of the comparator unit is connected to the output terminal of the s...
Embodiment 2
[0075] The present invention also provides a digital correction method, which is realized by adopting the digital correction circuit of the rapid convergence high-precision progressive analog-to-digital converter described in Embodiment 1. In particular, as one of the application scenarios of the present invention, when used for high-precision For SAR ADCs, combined with figure 1 As shown, it specifically includes the following steps:
[0076] Step STP100, input the input signal Vin into the first capacitance array unit (including the unit capacitance C through the switch Clks 1 -C N ), disconnect the switch Clks to complete the sampling;
[0077] Step STP200, receiving the result output from the comparator unit through the SAR control logic module to control the inversion of the first switch array unit to complete the conversion and quantization of the input signal Vin, and obtain the target quantization codeword;
[0078] Step STP300, close the switch Reset, and at the sa...
Embodiment 3
[0091] This embodiment is a further optimization scheme proposed on the basis of Embodiment 2. As mentioned above, if the calibration method in Embodiment 2 is used to carry out cyclic calibration, although fast convergence can be achieved, there is still room for improvement in terms of high precision, so the periodic iteration will produce the resulting periodic problem. Specifically, at every interval N+1 times, a cycle is completed. Due to the periodic operation of the capacitor array used and the digital circuit (specifically referring to all the circuit units used in the cycle), periodic disturbances will be generated on the power supply and reference voltage, which may generate periodicity in the output code word of the ADC Sexual glitches. In order to avoid this problem, in particular, on the basis of Embodiment 2, in order to avoid the glitch problem caused by periodic iterations, the method described in Embodiment 2 is optimized as follows: the current bit cell tha...
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