FPGA (Field Programmable Gate Array) chip layout method, device and equipment

Abstract

The embodiment of the invention provides an FPGA (Field Programmable Gate Array) chip layout method, device and equipment, and the method comprises the steps: obtaining a time delay lookup table matrix function Id (x, y) which represents the function relation of the time delay between circuit elements and the distance between the circuit elements, the time delay between the circuit elements comprises internal time delay of the source circuit element and the terminal circuit element and basic time delay between the internal time delay and the basic time delay, and the distance between the circuit elements comprises x and y which are the distances of an input pin j of the terminal circuit element relative to an output pin i of the source circuit element in the X direction and the Y direction respectively; converting the time delay lookup table matrix function Id (x, y) into a continuous matrix function; acquiring a continuous time delay penalty function T (x, y) through a continuous matrix function; and calculating the shortest time delay between the circuit elements based on the time delay penalty function T (x, y). According to the technical scheme provided by the embodiment of the invention, the time delays of all paths in the circuit can be quickly and accurately estimated, and the layout quality can be further improved from the time delays.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a method, device and equipment for field-programmable gate array (Field-Programmable Gate Array, FPGA) chip layout. Background technique [0002] The design process of FPGA chips mainly includes stages such as logic synthesis, technology mapping, packaging, layout, wiring, and bit stream generation. Among them, layout is a very complex and most critical stage, and its results directly affect circuit performance, area, and reliability. performance, power, and manufacturing yield. [0003] At present, the layout based on the FPGA chip uses its internal modules as the unit, and the bus length between the modules is used as the target to guide the placement of the unit during the layout process; although this method reduces the size of the unit, it reduces the flexibility of the layout. and may cause circuit delay violations. Contents of the invention [0004]...

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Problems solved by technology

[0003] At present, the layout based on the FPGA chip uses its internal modules as the unit, and the bus length between the modules is used as the target to guide the placement of the unit during the layout process; although this method reduces the size of the unit, it reduces the flexibility of the layout. and may cause circuit delay violations

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