3 results about "Matrix function" patented technology

The present invention discloses an incremental matrix multiplication accelerator for HPC / AI applications, comprising an HPC core, a Maidong accelerator core MZ, high-bandwidth memory HBM, global shared memory GSM, and a data bus. The Maidong accelerator core MZ includes a systolic array SA, a B buffer, and a C buffer. The B buffer is used to cache the matrix B required for matrix multiplication input to the systolic array SA, the C buffer is used to cache the matrix C required for matrix multiplication input to the systolic array SA, and the global shared memory GSM includes an A buffer for storing the matrix A required for matrix multiplication in the systolic array SA. The present invention can save storage resources without affecting performance, meet the bandwidth requirements of the systolic array, and can complete high-performance GEMM tasks simultaneously with the original HPC core without changing the original HPC core ecosystem and is compatible with the original matrix function library.

The application provides a linear scale electronic structure calculation method and system based on a dyeing superposition state and a terminal, based on the dyeing superposition state, and is used for solving sparse operator or matrix functions with spatial locality or limited correlation length, such as a density matrix, an inverse square root of an overlap matrix, and an operator required by an orthogonal representation transformation, which are involved in a Kohn-Sham self-consistent process under a local basis representation. On the premise of maintaining linear scale complexity, the application breaks through the dependence of a traditional algorithm on sparse matrix-sparse matrix multiplication (SpMSpM), and reconstructs core calculation into regular sparse matrix-dense matrix multiplication (SpMM). Through transformation of a bottom layer calculation paradigm, the regularity of Kohn-Sham electronic structure self-consistent calculation and the parallel adaptation ability of a bottom layer hardware are significantly improved, and inherent bottlenecks, such as a large pre-factor and low hardware execution efficiency, caused by the limitation of a core operator (SpMSpM) in a traditional linear scale algorithm are fundamentally relieved.