Integrated packaging structure based on TSV silicon switching substrate stacking and manufacturing method

Abstract

The invention discloses an integrated packaging structure based on TSV silicon switching substrate stacking and a manufacturing method, and belongs to the technical field of integrated circuit packaging. Comprising a TSV silicon switching substrate, a TSV silicon-based cavity switching substrate, a switching substrate interconnection structure, a TSV silicon switching substrate external solder ball, a first bottom filling structure, a second bottom filling structure, a microelectronic chip and a chip and switching plate interconnection structure. The TSV silicon-based cavity switching substrate is connected with the TSV silicon switching substrate through the interconnection structure between the switching substrates, the microelectronic chip is connected with the TSV silicon switching substrate through the chip and switching plate interconnection structure, the first bottom filling structure is located between the TSV microelectronic chip and the TSV silicon switching substrate, and the second bottom filling structure is located between the two substrates. According to the multi-chip integrated packaging structure, the system packaging size is reduced, the interconnection density is improved, the interconnection distance is shortened, the transmission delay is reduced, the bandwidth is improved, and the power supply efficiency is improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit packaging, and in particular relates to an integrated packaging structure and a manufacturing method based on stacking of TSV silicon transfer substrates. Background technique [0002] PoP, Packaging on Packaging, that is, stacked assembly, also known as stacked packaging. PoP adopts two or more BGAs, a packaging method in which ball grid array packages are stacked. Generally, the PoP stacked packaging structure adopts the BGA solder ball structure, and the digital or mixed-signal logic device is integrated at the bottom of the PoP package to meet the characteristics of multiple pins of the logic device. PoP packaging can realize multi-layer stacking, save the substrate area, and realize multi-chip integration in the vertical direction. [0003] The domestic patent "package-in-package device and its manufacturing method" patent number CN201310549390.3 discloses a package-in-package de...

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Problems solved by technology

[0004] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a multi-chip integrated package structure and manufacturing method based on TSV silicon transfer substrate stacking, so as to solve the problem of the small size of the TSV silicon transfer substrate and the limited number of integrated chips in the prior art. , low integration density in the Z-axis direction of the substrate, etc.

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