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FPGA-based high-speed Delay-FxLMS filter design method

A filter design and filter technology, applied in advanced technology, climate sustainability, sustainable communication technology, etc., can solve problems such as excessive adaptive delay m, system output lag, and algorithm convergence decline

Pending Publication Date: 2022-05-20
CHONGQING UNIV OF POSTS & TELECOMM
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Among the existing active noise control algorithms, the MATLAB simulation stage is the main one, and the DFxLMS algorithm itself has the problems of too large adaptive delay m and system output lag, which leads to a decline in the convergence of the algorithm

Method used

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Embodiment Construction

[0074] The technical solutions in the embodiments of the present invention will be described clearly and in detail below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some of the embodiments of the invention.

[0075] The technical scheme that the present invention solves the problems of the technologies described above is:

[0076] The invention discloses a FPGA-based high-speed Delay-FxLMS filter design method. It mainly includes three parts (1) DF-DFxLMS filter design (2) TF-RDFxLMS filter design (3) HS-TF-RDFxLMS filter design.

[0077] as attached figure 1 As shown, a kind of FPGA-based high-speed Delay-FxLMS filter design method proposed by the present invention is characterized in that, the DFxLMS filter specifically includes:

[0078] The adaptive filtering module is used to realize the multiplication operation of N weight coefficients and N input signals, and the DF-DFxLMS filter iteration formula is ...

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Abstract

The invention requests to protect a high-speed Delay-FxLMS filter design method based on an FPGA (Field Programmable Gate Array). The method mainly comprises three parts: (1) design of a DF-DFxLMS filter, (2) design of a TF-RDFxLMS filter, and (3) design of an HS-TF-RDFxLMS filter. The method is characterized in that a delay decomposition algorithm is adopted to solve the problem that the convergence of a filter is reduced due to delay increase and output lag, and then the adaptive filtering module and the secondary path module are subjected to transposition operation to further reduce a key path so as to improve the clock speed of the system. The number of registers of the whole circuit is reduced by optimizing the circuit sub-modules; and finally, on the premise that the critical path is not changed, the area / speed balance of the TF-RDFxLMS filter is realized by adopting a hardware sharing thought. Experimental results show that the convergence rate of the algorithm is 3.5 times that of a DFxLMS algorithm, a key path is shortened, the clock speed of an HS-TF-RDFxLMS filter is reduced by 4% compared with that of a TF-RDFxLMS filter, and LUT and FF resources are saved by 10% and 28% respectively.

Description

technical field [0001] The invention belongs to the field of digital signal processing, optimizes the algorithm and hardware structure of an adaptive filter, studies an adaptive filtering algorithm that is easy to realize by hardware, and proposes an FPGA-based high-speed Delay-FxLMS filter design method. Background technique [0002] Currently, the most popular adaptive algorithm used in Active Noise Control (ANC) systems is the Filtered-X Least Mean Square (FxLMS) algorithm. Small and easy to implement, it has become the "benchmark" algorithm in active noise control and is widely used. The core of the ANC system is an adaptive algorithm and an adaptive filter. The adaptive filter has a wide range of applications in the fields of system identification, inverse modeling, linear prediction and interference cancellation. With the development of integrated circuit technology, traditional algorithms implemented by software usually cannot meet the required processing speed. FPGA...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H21/00
CPCH03H21/0043H03H2021/0049Y02D30/70
Inventor 袁军袁财政孟祥胜赵强李军王巍王冠宇李勤
Owner CHONGQING UNIV OF POSTS & TELECOMM
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