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Non-volatile semiconductor memory device

A storage device, non-volatile technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, information storage, etc., can solve problems such as hindering low-voltage drive

Inactive Publication Date: 2004-12-08
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, after doing this, a voltage drop will be generated on the selection gate. In order to apply a high voltage to the control gate of the cell in the selected section when programming or erasing, it is necessary to increase the voltage of the voltage drop part
As a result, low-voltage driving is hindered, and it is not suitable for devices that require reduced power consumption, such as portable devices.

Method used

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Experimental program
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Embodiment Construction

[0036] Embodiments of the present invention are described below with reference to the drawings.

[0037] (memory cell structure)

[0038] FIG. 1 is a cross-sectional view showing a nonvolatile semiconductor memory device, and FIG. 2 is an equivalent circuit diagram showing it. In FIG. 1, a memory cell 100 includes a byte gate 104 formed on a P-type well (Well) 102 through a gate insulating film such as a two-layer structure (Polycide) of metal silicide and polysilicon (Polycide). , the second control gates 106A, 106B, and the first and second memory elements (MONOS memory cells) 108A, 108B.

[0039] The first and second control gates 106A and 106B are formed on both side walls of the byte gate 104, and are electrically insulated from the byte gate 104, respectively.

[0040] Each of the first and second storage elements 108A and 108B is made of one of the first and second control gates 106A and 106B formed of polysilicon corresponding to M (metal) of MONOS and a P-type well ...

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Abstract

A non-volatile semiconductor memory device having a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells controlled by a word gate and control gates, are arranged in first and second directions. The memory cell array region has a plurality of sector regions divided in the second direction. Each of a plurality of control gate drivers is capable of setting a potential of first and second control gates in the corresponding sector region independently of other sector regions. A plurality of switching elements which select connection / disconnection are formed at connections between a plurality of main bit lines and a plurality of sub bit lines.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor storage device comprising a storage unit including two nonvolatile storage elements controlled by one byte gate and two control gates. Background technique [0002] As a nonvolatile semiconductor memory device, it is known that the gate insulating layer between the channel and the gate is composed of a silicon oxide film, a silicon nitride film, and a laminated body of a silicon oxide film, and the charge is trapped on the silicon nitride film. MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type. [0003] This MONOS type nonvolatile semiconductor memory device is disclosed in literature (Y. Hayashi, et al. 2000 Symposium on VLSI Technology Digest of Technical Paper p.122-p.123). This document discloses a MONOS flash memory cell (flash memory) having two nonvolatile memory elements (MONOS memory cells) controlled by one byte gate and two control gates. That is, one flash memor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/02G11C16/04G11C16/06H01L21/8247H01L29/788H01L29/792H10B69/00
CPCH01L29/7923G11C16/0491G11C16/0475H01L27/115G11C16/3427H10B69/00
Inventor 金井正博龟井辉彦
Owner SEIKO EPSON CORP