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Method for evaluating inner connecting structure layout and sheet metal resistor thereof

A technology of structural layout and interconnection, applied in circuits, electrical components, electrical digital data processing, etc., can solve problems such as inability to accurately evaluate the electrical relationship of metal wires

Inactive Publication Date: 2006-06-14
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
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Problems solved by technology

However, due to the process characteristics of the copper process, the electrical relationship between the metal lines cannot be accurately evaluated only by the resistance of the metal sheet
[0005] Furthermore, due to the trend towards shrinking line widths and increasing densities in metal interconnect structures, the actual lithography of dense metal lines may create optical proximity when defining copper damascene trenches or contact holes in the dielectric layer. Effect (optical proximity correction)

Method used

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  • Method for evaluating inner connecting structure layout and sheet metal resistor thereof
  • Method for evaluating inner connecting structure layout and sheet metal resistor thereof
  • Method for evaluating inner connecting structure layout and sheet metal resistor thereof

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Embodiment Construction

[0012] In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and easy to understand, the following detailed description is as follows in conjunction with the accompanying drawings:

[0013] the following to figure 1 The flow of a method for evaluating the resistance of a metal sheet according to an embodiment of the present invention is described.

[0014] According to different products, semiconductor manufacturing plants usually provide several different process technology levels at the same time, which are generally determined by the optical capability or energy sensing capability of the lithography equipment. Micron, 0.18 micron or 0.13 micron etc. Due to different process technology levels, various steps and materials in the process technology have different combinations. Therefore, if figure 1 As shown, first proceed to step S102: select a predetermined process technology level. In this way, the main influencing...

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Abstract

A new method to determine a parameter of a damascene interconnect in an integrated circuit device is achieved. Drawn dimensions and local pattern density of a damascene interconnect are extracted in an integrated circuit device. A parameter of the damascene interconnect is calculating using the drawn dimensions and the local pattern density to select a per unit value from a set of per unit values measured over a range of drawn dimension and pattern density combinations. The method may be used to improve the accuracy of extracted damascene metal line resistance and parasitic capacitance.

Description

technical field [0001] The present invention relates to the layout design of integrated circuits, in particular to a method for evaluating the layout of the interconnection structure and its metal sheet resistance distribution. Background technique [0002] After the construction of the semiconductor upstream and downstream industrial division system is completed, the important role of the development of the IC design industry will be Electronic Design Automation (EDA). Among them, the general semiconductor design flow (Design Flow), including the front-end (Front-End) design architecture, behavior description, RTL (Register Transfer Level) program writing, GatesLevel logic circuit, each stage has undergone repeated synthesis, simulation, and verification , debug, etc. until complete. After that, physical circuit layout (Layout) and wiring work need to be carried out through the back-end (Back-End). At this stage, process requirements need to be considered, such as high-pe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/82H01L21/768H01L21/66G06F17/50
CPCG06F30/367
Inventor 庄学理张智援陈永顺侯上勇
Owner TAIWAN SEMICON MFG CO LTD
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