Phase detector

Abstract

There is disclosed a phase detector which triggers on both rising and falling edges of an input pulse signal. This effectively doubles the frequency of the input signal. When the phase detector is used in a phase locked loop, the doubled frequency means that a lower division ratio can be used, thereby reducing any noise contribution introduced thereby.

Description

[0001] technical field of invention [0002] The present invention relates to a phase detector circuit, and more particularly to a phase detector which can be used in a phase-locked loop. More specifically, the present invention relates to a phase detector that is triggered on both edges of a system clock, thereby effectively doubling the reference frequency without adding circuitry and noise. Background of the invention [0003] In digital communication systems, such as mobile telephone communications operating under the GSM or DCS systems, continuous phase modulation (CPM) techniques are used. [0004] Phase locked loops are well known. A signal with a reference frequency provides the input to the phase detector, and the output of the phase detector is filtered and sent to the voltage controlled oscillator. The output of the voltage controlled oscillator is the output of the phase locked loop and is also fed back to the frequency divider. The output of the frequency divid...

AI Technical Summary

Problems solved by technology

However, introducing, such as a frequency multiplier to increase the reference frequency and reduce the influence of noise, requires additional circuitry, and increases the scale and current consumption of the circuit

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