Sidewall spacer for semiconductor device and fabrication method thereof

Abstract

An offset spacer layer for an LDD ion implantation process is formed by blanket deposition without photolithography and dry etch processes. The offset spacer layer remaining on LDD regions during an ion implantation process prevents a substrate from silicon loss and dosage contamination and has densified characteristics to improve device reliability.

Description

technical field [0001] The present invention relates to a metal oxide semiconductor (MOS) device, and more particularly to a MOS device with offset spacers to improve deep sub-micron processes. Background technique [0002] The development trend of very large scale integration (VLSI) is to use larger silicon chips with smaller line widths so that more functions can be integrated into a fixed-sized integrated circuit. Continuously designed semiconductor components such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) for improved current efficiency take up less physical space, consume less power and operate at lower voltages with faster switching speeds, and The miniaturization of MOS devices brings the source and drain terminals closer to each other. When the channel length is shortened, the overlap between the depletion region in the source / drain terminal and the channel is increased, and the shortening of the channel length often leads to Accompanied by hot...

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Problems solved by technology

[0006] The above-mentioned formation of the compensation spacer traditionally includes deposition and dry etching methods, which are poor in stability, high in cost and complicated; and when the element size is reduced to less than 0.13 microns, the method application range (process window) of the deposition and etching methods will be reduced. become smaller, and the size change can easily affect the critical dimension (CD for short) and the electrical performance of MOSFET components; and after the dry etching method to compensate for the formation of spacers, the wet chemical immersion (such as Caro acid) to strip the oxide method will damage the silicon substrate surface and cause silicon loss, and this situation will be more serious after the wet cleaning of the subsequent LDD implantation is performed; in addition, the activated LDD after the ion implantation method 22 The high temperature annealing step of the region 24 dopant has dopant control and dopant contamination issues to be overcome

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