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A CMOS circuit structure situated on SOI substrate and manufacturing method thereof

A technology of circuit structure and fabrication method, applied in circuits, electrical components, electrical solid devices, etc., can solve the problem that bulk silicon technology is no longer applicable, and achieve the effects of flexible circuit layout design, reduced length, and high scalability

Active Publication Date: 2007-01-31
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

But after 50nm technology, bulk silicon technology will no longer be applicable, and new technologies must appear to replace it

Method used

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  • A CMOS circuit structure situated on SOI substrate and manufacturing method thereof
  • A CMOS circuit structure situated on SOI substrate and manufacturing method thereof
  • A CMOS circuit structure situated on SOI substrate and manufacturing method thereof

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Embodiment Construction

[0044] The CMOS structure proposed by the present invention consists of figure 1 , figure 2 and image 3 shown. in figure 1 is a three-dimensional structure, figure 2 and image 3are the corresponding cross-sectional structures.

[0045] The CMOS structure is formed on a single crystal silicon substrate 1 and is isolated from the substrate 1 by a buried oxide layer 2 .

[0046] The CMOS structure is composed of a polysilicon electrode 9 , a gate dielectric layer 8 , an upper silicon ingot (4+20+7), a lower silicon ingot (3+10+5) and an insulating layer 6 between silicon ingots. Wherein, the lower silicon ingot (3+10+5) is located on the buried oxide layer 2 , the insulating layer 6 is located on the lower silicon ingot, and the upper silicon ingot (4+20+7) is located on the insulating layer 6 . The gate dielectric layer 8 is located on the top and both sides of the upper silicon ingot (4+20+7) and on both sides of the lower silicon ingot (3+10+5). The polysilicon ele...

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Abstract

The invention supplies a CMOS circuit structure on SOI substrate, comprising gate electrode, gate dielectric layer, active area of upper-and-lower silicon ingot and isolated insulating layer between active area of upper-and-lower silicon ingot; the lower layered silicon ingot is on oxide layer covered at the bottom of substrate, gate dielectric layer is on the top of active area of the upper-layered silicon ingot and its two sides and the two sides of active area of the lower-layered silicon ingot; gate electrode is on gate dielectric layer, upper-layered silicon ingot, lower-layered silicon ingot and component formed by isolated insulating layer between silicon ingot, with the bottom on covered oxide layer of substrate. The CMOS structure has excellent reducible ability , high density of combination integration density and notably reduces wires and their lengths. Besides, it supplies the manufacture method of the CMOS circuit which includes the steps like oxygen injection and annealing on the SOI substrate form double active layer.

Description

Technical field: [0001] The invention belongs to the field of semiconductor integrated circuit (IC) and its manufacturing technology, in particular to a CMOS circuit structure on an SOI substrate and a manufacturing method thereof. Background technique: [0002] Since the invention of the integrated circuit, its development has been precisely following Moore's law, that is, a new generation of new technology is produced every 2-3 years. Each new generation of technology results in a triple increase in logic circuit density, a 40% improvement in performance, and a quadruple increase in storage capacity. And all of this is mainly achieved by continuously shrinking the device size and increasing the chip area. [0003] On the other hand, as integrated circuit technology enters the nanometer era or the feature size of the device shrinks to the nanometer scale, the integrated circuit itself is also developing towards the system integration level, which leads to the system chip (...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L27/092H01L21/84H01L21/8238
Inventor 张盛东陈文新吴旭升韩汝琦
Owner SEMICON MFG INT (SHANGHAI) CORP
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