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Forming method of oblique inlaid inner connection structure of integrated circuit

An integrated circuit and interconnection technology, applied in the field of dual damascene structure improvement

Inactive Publication Date: 2007-02-07
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Therefore, how to solve the defects caused by the high aspect ratio and sharp corners of the damascene structure existing in the manufacturing process of the existing integrated circuit with multiple interconnected dual damascene structures is the technology to be solved by the present invention. question

Method used

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  • Forming method of oblique inlaid inner connection structure of integrated circuit
  • Forming method of oblique inlaid inner connection structure of integrated circuit
  • Forming method of oblique inlaid inner connection structure of integrated circuit

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Embodiment Construction

[0018] The invention discloses a method for forming a dual damascene interconnect structure. Specifically, the invention provides a method for manufacturing sloped dual damascene interconnect structures and provides an embodiment thereof. The detailed description is as follows, and the preferred embodiments are only for illustration and not for limiting the present invention.

[0019] Please refer to figure 1 , in a preferred embodiment, a structure 100 with a copper plug 101 is provided. Next, a dielectric layer 102 is formed on the copper metal plug 101, and the dielectric layer 102 is a silicon nitride layer formed of silicon nitride. Generally speaking, the above-mentioned silicon nitride layer 102 can be formed by a suitable procedure, such as chemical vapor deposition, at a temperature of about 700 to 1100° C. and in an environment filled with nitrogen. In a specific embodiment, the thickness of the dielectric layer 102 is about 100˜250 angstroms.

[0020] Please refe...

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Abstract

The method includes steps: forming first dielectric layer on a structure of copper metal plug; next, forming an insulating layer on the said first dielectric layer; then, forming second dielectric layer composed of at least one layer in low dielectric constant on the said insulating layer; first time of etching the second dielectric layer, the insulating layer and first dielectric layer so as to form a dielectric hole (via) above the said copper metal plug; finally, second time of etching the said second dielectric layer and the insulating layer in order to form the invented structure.

Description

technical field [0001] The invention relates to an improvement of a dual damascene (Dua1 damascene) structure with multiple interconnections in integrated circuits, in particular to a method for forming sloped dual damascene interconnect structures. Background technique [0002] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is an important component in integrated circuits. However, with the continuous progress of integrated circuits, many problems have been encountered in the manufacture of MOSFETs. Typical problems such as hot carrier effects have been solved by The development of Lightly Doped Drain (LDD) structures overcomes this. However, as the size of transistors shrinks to sub-micron, the problem of hot electrons recurs due to the shortened channels of transistors and higher power consumption. And as the electric field strength in the device increases, electrons with high energy will be injected into the silicon layer-oxide junction and trapped in the ga...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/31H01L21/3205
Inventor 汪钉崇
Owner SEMICON MFG INT (SHANGHAI) CORP
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