Method of avoiding noise interference of sync switch in circuit system design

Abstract

The method of avoiding noise interference of sync switch in circuit system design includes at least the following steps: calculating the delay Td between the sending clock and the receiving clock of the chip and the maximum error tolerance Tyd of the delay; determining the allocation scheme of delay in different circuit parts; increasing a phase-locking loop circuit; simulating the delay of different circuit parts; judging whether the delay in different circuit parts fulfills the requirement; and regulating the phase-locking loop circuit or wire length to control delay and delay error or repeating the steps of determining the allocation scheme and calculating line delay error range in case of obtaining simulating result not meeting the requirement.

Description

technical field [0001] The invention is applied to the field of complex and high-speed circuit system design, and in particular relates to a method for avoiding synchronous switch noise interference in complex and high-speed circuit systems. Background technique [0002] At present, the design of the circuit system tends to be complex, and as the circuit system runs faster and faster, its operating frequency is also getting higher and higher. It is precisely because of the increase in the system operating frequency that it will inevitably affect the stability of the system operation. problem, and synchronous switching noise (Synchronous-SwitchingNoise) interference is one of the more prominent problems, the reason is: the size of the synchronous switching noise is proportional to the driving ability of the signal (that is, the steepness of the signal edge), when the circuit system is at a low frequency, Although the timing requirements of the synchronous circuit system are r...

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Problems solved by technology

[0002] At present, the design of the circuit system tends to be complex, and as the circuit system runs faster and faster, its operating frequency is also getting higher and higher. It is precisely because of the increase in the system operating frequency that it will inevitably affect the stability of the system operation. problem, and synchronous switching noise (Synchronous-SwitchingNoise) interference is one of the more prominent problems, the reason is: the size of the synchronous switching noise is proportional to the driving ability of the signal (that is, the steepness of the signal edge), when the circuit system is at a low frequency, Although the timing requirements of the synchronous circuit system are relatively loose (negligible), for the asynchronous circuit system, its impact needs to be considered. Specifically, for the asynchronous circuit system, when it operates at a higher frequency, As the rising and falling edges of the signal become steeper and the signal period becomes shorter, the synchronous switching noise (SSN) interference increases rapidly. At this time, if there are many output signals that the chip pins jump at the same time, the synchronous switching noise will be superimposed. As a result, the sampling reference level of the chip in the system floats to the point where the signal sampling is inaccurate, which is precisely an important factor for the high-speed system to not work stably

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