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Method for reducing software load of system-on-chip (SoC)

A system-on-chip and software technology that is applied in the computer field to achieve strong versatility, reduce the number of interruptions, and solve the effect of increasing software load

Inactive Publication Date: 2007-08-22
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the specific I / O channel implementation method is not mentioned in the book

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  • Method for reducing software load of system-on-chip (SoC)
  • Method for reducing software load of system-on-chip (SoC)

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Embodiment Construction

[0016] The present invention will be further described below in conjunction with accompanying drawing:

[0017] The present invention is accomplished jointly by software and hardware. The software is responsible for organizing the instructions into a linked list and controlling the startup and reset of the hardware.

[0018] As shown in Figure 1, the instruction linked list is organized as follows: an instruction node is composed of an instruction word, all parameters and NIP (used to store the starting memory address of the next node), and they are stored continuously in the memory, assuming the address of the instruction word is X, and there are N parameters in total, then their addresses are X, X+1, X+2...X+N+1 in turn. The last NIP is a pointer to the next node, and it is agreed that if the value of this unit is 0, it means that this node is the last node of the linked list. One node corresponds to one operation, multiple nodes form an instruction linked list, and the NI...

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PUM

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Abstract

The invention relates to a method for relieving the chip system software loading in the field of a computer technology. The invention adopts link list theorem; the software responsible for organizing a plurality of operation order into a link list and controlling the hardware start and return; it automatically reads hardware into each point of the link list after starting the hardware to finish the data operation and sends a discontinue signal after the entire order link list is carried out. It uses the order character and the entire parameters to form an order point, each pint is correspondent with an operation, the last NIP is a pointer to the next point which can store the internal memory address of the next point and if the unit value is zero, the point is the last point, a plurality of points can form an order link list.

Description

technical field [0001] The invention relates to a method in the field of computer technology, in particular to a method for reducing the software load of an on-chip system. Background technique [0002] A system on chip (SoC) usually consists of a system framework (including CPU, bus, storage unit, etc.) and multiple input / output (I / O) functional modules. Among them, the CPU is responsible for the control of various I / O functional modules (such as audio module, video decoding module, video processing module, graphics system module, etc.), and this control is generally completed by configuring the registers of each I / O functional module. These registers are usually located in the host control interface module (HostIF), and are uniformly addressed with the system memory, and generally include control registers, instruction registers and parameter registers. The control register completes the reset and start control of the I / O function module. The instruction register indicat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/46G06F9/44
Inventor 朱建清郑世宝顾亮王峰张文军
Owner SHANGHAI JIAO TONG UNIV
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