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Semiconductor device

A semiconductor and device technology, applied in the field of vertical semiconductor devices, can solve problems such as low breakdown voltage, high on-resistance and high loss

Inactive Publication Date: 2003-01-15
FUJI ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, because n - type drift layer 12 is depleted in the off-state of the device, such that n - type drift layer 12 vits for this voltage, reducing its resistivity by heavily doping n - type drift layer 12, or a thin n - type drift layer 12 can produce low breakdown voltage values
[0008] To obtain semiconductor devices with high breakdown voltage values, thicken n - type drift layer 12, it will inevitably produce high on-resistance and high loss

Method used

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  • Semiconductor device
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Examples

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no. 1 example

[0204] figure 2 It shows a cross-sectional view showing a part of the active region of the n-type channel vertical MOSFET according to the first embodiment of the present invention, in which the main current flows. A breakdown bearing structure such as a guard ring and a field plate, which is inserted in the peripheral portion of the MOSFET semiconductor chip, will be described later.

[0205] now refer to figure 2 , the MOSFET according to the first embodiment includes a layer of n with low impedance + type drain layer 11, a layer with high resistivity n - type drift layer 12, located at n + Type drain layer 11, p-type well region 13, selectively in n - type drift layer 12 surface part is formed, and n + The p-type source region 15 is in the p-type well region 13. multiple n - Type surface region 14 extends to the surface of the semiconductor chip through p-type well region 13, the n - Type surface area 14 is n - part of the drift layer 12. heavily doped p + Type...

no. 2 example

[0253] Figure 17 A cross-sectional view is shown showing the active region of an n-channel vertical SFET according to a second embodiment of the present invention. Figure 18 A perspective view is shown showing the active region of the n-type channel vertical MOSFET according to the second embodiment.

[0254] The vertical MOSFET according to the second embodiment is different from the vertical MOSFET according to the first embodiment in that the n-type counter-doped region 34 is formed on the p-type well region 13 of the MOSFET according to the second embodiment instead of According to the MOSFET of the first embodiment n - type surface region 14 formed on, figure 2 shown.

[0255] By injecting 2.0×10 12 to 5.0×10 12 cm -2 , preferably 2.5×10 12 to 4.0×10 12 cm -2 Dosage of phosphorus ions and sequential heat treatment to form n-type counter-doped region 34 . The depth of the n-type counter-doped region 34 is about 4 microns. By forming the n-type counter-doped r...

no. 3 example

[0261] Figure 20 A cross-sectional view is shown showing the breakdown carrying region of an n-channel vertical MOSFET according to a third embodiment of the present invention.

[0262] The breakdown carrying structure of the vertical MOSFET according to the third embodiment is different from that of the reference Figure 13 The structure of the described MOSFET according to the first embodiment is that the breakdown carrying structure according to the third embodiment includes six guard rings and an electrically conductive polysilicon film 35 formed on the field oxide film 17a between adjacent p-type guard rings. .

[0263] A voltage should be applied between the drain 20 and the source 19 when the device is actually used. Factors that adversely affect stability when this voltage is applied for a long time include accumulation of charge on the surface of the device (surface charge accumulation effect). When a voltage is also applied between the electrodes at the two ends of...

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Abstract

The present invention discloses a semiconductor device which has high dielectric strength and low ON-resistance, and can switch at a high speed by improviding the trade-off relation between the dielectric strength and the ON-resistance. Resistivity p (Omega cm) of a voltage base layer 12 of a longitudinal semiconductor with a dielectric strength Vbr lies in the range such that -5.34+0.0316 Vbr < Rho <-1.86+0.0509 Vbr. Furthermore, the surface of an n<-> surface region 14 as the surface exposed part of an n<-> drift layer 12 with high resistivity is striped, while surrounded with a p well region 13 and the region ratio of the n<-> surface region 14 to the area of a p well area 13 including the n<+> source region 15 is 0.01 to 0.2.

Description

technical field [0001] The present invention relates to semiconductor devices, such as MOS type field effect transistors (hereinafter referred to as (MOSFET's) and insulated gate bipolar transistors (hereinafter referred to as IGBT's), which contain a metal (M) formed gate structure, One layer of oxide film (O) and a semiconductor layer (S). The present invention relates especially to vertical (vertical) semiconductor device, and this device shows high breakdown voltage and low power consumption, comprises the electrode on the main surface of semiconductor chip, and makes Current flows vertically between the electrodes. Background technique [0002] In general, vertical semiconductor devices in which current flows between electrodes on the main surface of a semiconductor chip are widely used in power semiconductor devices. Figure 31 A cross-sectional view showing the active region of a conventional planar N-channel vertical MOSFET through which the main current flows. [0...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/08H01L29/423H01L29/78
CPCH01L2924/0002H01L29/0847H01L29/0634H01L29/402H01L29/7802H01L29/0696H01L29/0619H01L29/4238H01L2924/00
Inventor 藤平龙彦小林孝阿部和新村康井上正范
Owner FUJI ELECTRIC CO LTD