Semiconductor memory

Abstract

Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions to implement high speed memory in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines. Thereby, it becomes unnecessary to separately provide strapping regions at the ends of memory cell array portions and it becomes unnecessary to increase the intervals between the memory cells by increasing the size of the memory cell in the layout according to the standard CMOS process and, therefore, contacts for strapping word lines can be provided for each memory cell, without increasing the area of memory cell array portions or the chip area, so that the propagation delay of drive signals in word lines can be reduced and high speed memory operation can be implemented.

Description

field of invention [0001] The present invention relates to semiconductor memory devices. Background technique [0002] Figure 4 A layout diagram showing a DRAM (Dynamic Random Access Memory) memory cell array, one of semiconductor memory devices designed using a conventional DRAM hybrid process. Figure 4 Among them, 1 (1a to 1h) is a bit line formed by the first-layer aluminum wiring. 2 is a word line disposed in a direction crossing the bit line and operating as a gate of a transistor selectively connecting the memory cell to the bit line, which is formed of polysilicon wiring. In addition, 3 is a bit line contact electrically connecting the bit line 1 and the memory cell transistor 5, 4 is a memory cell capacitor, and 5 is a memory cell transistor. Reference numeral 6 denotes a 1Tr1C type memory cell arranged at intersections of word line 2 and bit line 1 and composed of memory cell capacitor 4 and memory cell transistor 5 . Memory cell 6 is connected to word line 2 and...

AI Technical Summary

Problems solved by technology

In addition, since the contact (substrate contact) for the substrate connection is formed on the same wiring layer as the bit line (for example, the first layer of aluminum wiring), there is a disadvantage that in order to ensure the placement of the substrate contact in each memory cell, Space, the entire memory cell size must be enlarged and the memory cell pitch must be increased, and the distance between bit lines needs to be enlarged

[0006] That is, in recent years, in order to achieve high integration and large capacity of DRAM, the capacitor structure of the storage unit has changed from the previous planar type to the stacked (stacked) type or trench ( Groove) three-dimensional structure realizes the miniaturization of the memory cell structure. The reverse side is that the space between the bit lines is reduced. It is not possible to set up a lining contact in each memory cell, but to set a lining area at the end of the memory cell array and use a lining connection.

[0007] Like this, in order to make high-speed storage possible, it is necessary to adopt a word line bonding structure that can suppress the signal delay of the word line formed by high-resistance polysilicon. However, just because of this, it is necessary to additionally set the bonding area at the end of the memory cell array As a result, the area of ​​the memory cell array increases

[0008] Furthermore, in the past, the power supply line for supplying the power supply voltage to each memory cell is formed by the upper wiring layer on the bit line, and since the contact is drawn out from the upper power supply line to supply the power supply voltage to each memory cell, the IR drop increases.

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