Memory with two-stage read-out amplifier carrying extra load unit

A load unit and memory technology, applied in the field of memory, can solve the problems of transient time extension, long time, operating margin, and reading speed.

Inactive Publication Date: 2003-11-05
EMEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] However, as known from known technologies, if the aspect ratio of the transistor Ta1 is reduced, the current driving capability of the transistor Ta1 will also be reduced, so that the transient time in the reading process will be prolonged; that is, from the storage The unit starts to supply data current to pull down the voltage of the first comparison terminal. When the voltage of the first comparison terminal reaches a steady

Method used

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  • Memory with two-stage read-out amplifier carrying extra load unit
  • Memory with two-stage read-out amplifier carrying extra load unit
  • Memory with two-stage read-out amplifier carrying extra load unit

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Embodiment Construction

[0049] refer to Figure 5 . Figure 5 It is a schematic circuit diagram of the memory 30 in the present invention. The memory 30 is biased with a DC power supply Vdd, and is provided with a plurality of memory cells ( Figure 5Two memory cells 31A, 31B are depicted in the figure), load isolation cells 32A and 32B, metal oxide semiconductor transistor M1 as the first load cell, second load cell 36A, readout unit SA, equalization unit 34, The metal-oxide-semiconductor transistor M3 as the third load unit, the fourth load unit 36B, and the metal-oxide-semiconductor transistor M7 as a reference unit. The memory cells 31A and 31B use metal-oxide-semiconductor transistors Mm1 and Mm2 with floating gates to store data. The transistors MA1 and MA2 respectively control the data access of the memory cells 31A and 31B. The gates of the transistors Mm1 and Mm2 are respectively controlled by the control voltages Vm1 and Vm2 to bias voltages; the gates of the transistors MA1 and MA2 are ...

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Abstract

The memory includes at least one memory unit for storing data and providing data current; one relatively weak first load unit with one first end; one relatively strong second load unit with one second end; and one read-out unit. The first load unit and the second load unit can accept current input to establish voltage in the first end and the second end separately. When the memory unit providesdata current, the relatively strong second load unit will be first used and the data current will be fed to the load unit and the second load unit.After being used for some set time, the second load unit will be disabled and the data current will be fed to the relatively weak first load unit rather than the second load unit. The read-out unit will produce data signal based on the difference between the first end voltage and the reference voltage, so that the memory will read out the data stored in the memory unit.

Description

technical field [0001] The present invention provides a method related to a non-volatile memory, especially a method for accelerating the transient process of the memory by using an additional load element when reading data, and then disabling the load element to maintain data reading sensitivity and margin memory and related methods. Background technique [0002] With the vigorous development of the information society, a large amount of data, data, technology and even knowledge can be organized and stored in the form of digital data; and the memory used to store digital data has become the focus of research and development in the information industry. In particular, flash memory (flash memory) can store digital data in a non-volatile manner and can be quickly accessed electronically. Unlike ordinary hard disks that require mechanical action parts, it has become the most important non-volatile memory. One of the volatile storage devices. [0003] r...

Claims

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Application Information

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IPC IPC(8): G11C7/00G11C16/06
Inventor 许佑铭胡凌彰
Owner EMEMORY TECH INC
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