Memory with two-stage read-out amplifier carrying extra load unit

Abstract

The memory includes at least one memory unit for storing data and providing data current; one relatively weak first load unit with one first end; one relatively strong second load unit with one second end; and one read-out unit. The first load unit and the second load unit can accept current input to establish voltage in the first end and the second end separately. When the memory unit providesdata current, the relatively strong second load unit will be first used and the data current will be fed to the load unit and the second load unit.After being used for some set time, the second load unit will be disabled and the data current will be fed to the relatively weak first load unit rather than the second load unit. The read-out unit will produce data signal based on the difference between the first end voltage and the reference voltage, so that the memory will read out the data stored in the memory unit.

Description

technical field [0001] The present invention provides a method related to a non-volatile memory, especially a method for accelerating the transient process of the memory by using an additional load element when reading data, and then disabling the load element to maintain data reading sensitivity and margin memory and related methods. Background technique [0002] With the vigorous development of the information society, a large amount of data, data, technology and even knowledge can be organized and stored in the form of digital data; and the memory used to store digital data has become the focus of research and development in the information industry. In particular, flash memory (flash memory) can store digital data in a non-volatile manner and can be quickly accessed electronically. Unlike ordinary hard disks that require mechanical action parts, it has become the most important non-volatile memory. One of the volatile storage devices. [0003] r...

AI Technical Summary

Problems solved by technology

[0010] However, as known from known technologies, if the aspect ratio of the transistor Ta1 is reduced, the current driving capability of the transistor Ta1 will also be reduced, so that the transient time in the reading process will be prolonged; that is, from the storage The unit starts to supply data current to pull down the voltage of the first comparison terminal. When the voltage of the first comparison terminal reaches a steady state and the data can be read, it will take a long time (equivalently, it takes a long time to Discharge the charge accumulated at node Na1)

In this way, the memory cannot read data quickly, reducing the efficiency of data access

However, in the known transistor 10 or 20, because of the design of the load unit (i.e., the transistor Ta1), there are problems that the above-mentioned operation margin and reading speed cannot be balanced.

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