[0047] Figure 2a to 2e A schematic cross-sectional view of a method for manufacturing a shallow trench (STI) structure that avoids acute angles according to a preferred embodiment of the present invention.
[0048] See Figure 2a , A silicon oxynitride (SiON; silicon oxynitride) 12 and a shielding layer 13 are sequentially formed on a semiconductor substrate 10. The semiconductor substrate is, for example, a silicon substrate. The method of forming the SiON layer 12 is: for example, using SiH 4 , N 2 O, N 2 The reaction gas is formed by low pressure chemical vapor deposition (LPCVD; low pressure chemical vapor deposition) or plasma-enhanced chemical vapor deposition (PECVD; plasma-enhanced chemical vapor deposition), and the thickness can be between 150 Ȧ and 250 Ȧ . The shielding layer 13 can be a silicon nitride layer, and dichlorosilane (SiCl 2 H 2 , Dichlorosilane) and NH 3 The reaction gas is formed by the LPCVD method, and the thickness can be between 1500 angstroms and 2500 angstroms.
[0049] Next, a patterned photoresist layer (not shown) is formed on the shielding layer 13 to define the active area of the device to be formed in the future. Using the patterned photoresist as a mask, the SiON layer 12 and the shielding layer 13 are etched anisotropically to form an opening 20 to expose the part of the substrate where the shallow trench isolation region is to be formed, and then the photoresist is removed.
[0050] reference Figure 2b CVD method is used to deposit a compliant oxide layer (not shown), such as a silicon oxide layer, with a thickness of 400 Ȧ to 500 Ȧ to cover the entire surface of the semiconductor substrate 10. Next, the compliant oxide layer is etched anisotropically, and an oxide spacer 32 is formed on the sidewalls of the SiON layer 12 and the shielding layer 13. Next, using the oxide spacer 32 and the shielding layer 13 as a mask, the exposed semiconductor substrate 10 is etched to form a channel 21. The etching step may use dry etching, such as reactive ion etching (RIE), and the depth of the trench 21 may be about 0.1 μm to 1.5 μm.
[0051] reference Figure 2c , A pad oxide layer 34 is formed on the surface of the trench 21 by a thermal oxidation method. For example, the silicon substrate 10 is placed in a furnace tube with a temperature of 800° C. to 1100° C., and oxygen is introduced. The thickness of the pad oxide layer 34 may be 400 Ȧ to 800 Ȧ. When the silicon substrate is subjected to the thermal oxidation manufacturing method, the oxidation will not only proceed on the exposed area, but also on the unexposed area. Therefore, oxygen diffuses into the SiON layer 12, and the bird's beak structure 36 is formed like the LOCOS manufacturing method. In addition, during the thermal oxidation process of the pad oxide layer 34, two different materials will be encountered, namely the SiON layer 12 and the oxide spacer 32. Therefore, the oxidation (in the vertical direction) towards the oxide spacer 32 will be faster than the oxidation (in the lateral direction) towards the SiON layer 12. Therefore, the beak structure is thick in the vertical direction and short in the lateral direction. Moreover, due to the bird's beak structure, the apex angle (referred to as the channel apex angle) 50 formed by the vertical sidewall 16 and the upper surface 18 of the silicon substrate 10 becomes round.
[0052] reference Figure 2d , An isolation oxide layer is filled into the trench 21. For example, using oxygen (O 2 ) And silane (SiH 4 ) Is a reactive gas, and an oxide layer is deposited on the entire surface of the semiconductor substrate 10 by means of high-density plasma chemical vapor deposition (HDPCVD; high-density plasma chemical vapor deposition), and the HDP oxide layer is filled into the trench 21 . Next, a planarization manufacturing method, such as a chemical mechanical polishing method, is performed on the HDP oxide layer until the shielding layer 13 is exposed. in Figure 2d Here, the oxide spacer 32, the pad oxide layer 34 and the filled isolation oxide layer are integrated into the integrated oxide layer 30 in the trench 21. Next, the shielding layer 13 and the SiON layer 12 are removed. Thus, formed Figure 2e In the structure shown, an integrated oxide layer 30 is filled in the trench 21, and the top corner 50 of the trench is round.
[0053] In summary, the present invention uses the SiON layer 12 as a liner layer, and forms oxide spacers 32 on the sidewalls of the SiON layer 12 and the shielding layer 13. Therefore, when the pad oxide layer 34 is formed on the surface of the channel 21 by the thermal oxidation method, since the oxidation (in the vertical direction) toward the oxide spacer 32 is faster than the oxidation (in the lateral direction) toward the SiON layer 12, Can form a thick and short beak structure. The channel apex angle 50 formed by the vertical sidewall 16 and the upper surface 18 of the silicon substrate 10 becomes rounded. Therefore, when a dielectric material, such as a tunnel oxide layer, is formed on the active region, due to the rounded top corner 50, the top corner thinning effect can be avoided. The thickness of the tunnel oxide layer is uniform and its integrity can be maintained. Therefore, the electric field is not concentrated at the top corner of the channel, and parasitic transistors and leakage can be avoided.
[0054] Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make equivalent changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention is subject to the claims.
