Semiconductor device with high structure reliability and low parasitic capacitance

Abstract

A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.

Description

technical field [0001] The present invention generally relates to semiconductor devices excellent in high-frequency operation, and in particular to semiconductor devices with high structural reliability and as low parasitic capacitance as possible. Background technique [0002] A heterojunction bipolar transistor disclosed in JP-A 177966 / 1987 (Prior Art 1) is known as an existing structure of a semiconductor device excellent in high-frequency operation. In the device structure of prior art 1, on a semi-insulating GaAs substrate, an emitter layer including a wide-bandgap N-type semiconductor layer, a base layer including a P-type semiconductor layer, and A collector layer comprising an N-type semiconductor layer, wherein a collector electrode using an AuGe alloy is provided on the uppermost layer, a base electrode using an AuZn alloy is provided on the base layer exposed by etching, and on the back of the semi-insulating GaAs substrate After polishing, the emitter electrode ...

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Problems solved by technology

[0005] However, as described above, when mesa etching is performed for device isolation in the structure of prior art 1, in the backside etching step of forming a via hole from the backside inside the transistor region to arrange the conductive region of the emitter electrode, if the via If the hole and mesa corrosion area are not strictly aligned, the yield will be reduced

Moreover, when a large alignment margin is used in order to avoid reducing the yield, the chip area increases, resulting in an increase in chip cost

[0006] Although prior art 2 does not require the electrode contact area to be set within the transistor area, the trench on the back side is made larger, and the area of ​​the thin area of ​​several microns increases, which may reduce the mechanical strength

[0007] Moreover, in both the prior art 1 and the prior art 2, an organic adhesive such as epoxy paste is used for bonding on the chip bonding, and a solvent is generated in the through hole due to heating and drying of the adhesive. vapor, so the pressure inside the via increases, sometimes damaging the semiconductor region on the via

[0008] And, this will result in a structure where a thin semiconductor layer of a maximum of several μm or less is left near the electrode contact region, for example, the stress applied to the chip bonding due to the increased pressure in the via hole is concentrated in the thin Semiconductor regions, causing crystallization to crack, expand until transistor regions fail due to chip damage or transistor damage

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