Method of forming light doped drain electrode using side wall polymer grid structure

A lightly doped drain and gate structure technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as affecting the stability of components, difficulty in manufacturing semiconductor components, and shortening channel lengths

Inactive Publication Date: 2004-02-18
GRACE SEMICON MFG CORP
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Problems solved by technology

[0004] However, in the subsequent thermal process of the LDD 24, the ions of the LDD 24 often diffuse laterally due to heating, such as Figure 1C As shown, the diffusion to the position below the polysilicon gate 14 invades the channel region and shortens the length of the channel. This phenomenon will cause leakage current, punch through effect and shallow ion doping between the polysilicon gate and The short channel effect such as the parasitic capacitance (parasitic capacitor) in the miscellaneous area is particularly significant in the sub-micron process (less than 0.15μm process)
[0005] Therefore, in the face of higher and higher component integration and smaller and smaller process line widths, the lateral diffusion of LDD caused by the subsequent thermal process will not only shorten the channel distance, but will further form the short channel effect of the components. , which will affect the stability of components, will make it difficult to make smaller semiconductor components, and reduce the yield and electrical quality of components

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  • Method of forming light doped drain electrode using side wall polymer grid structure
  • Method of forming light doped drain electrode using side wall polymer grid structure
  • Method of forming light doped drain electrode using side wall polymer grid structure

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Embodiment Construction

[0013] The present invention pre-forms a sidewall polymer (sidewall) on the substrate, so that after the shallow ion doped region is formed, the shallow ion doped region only diffuses laterally to the substrate under the sidewall polymer during thermal processing , when forming the LDD structure, the length of the channel can be precisely controlled, effectively solving the common short channel effect in the semiconductor manufacturing process.

[0014] Figure 2A to Figure 2F The schematic cross-sectional views of each step of making the LDD for a preferred embodiment of the present invention are respectively; as shown in the figure, the manufacturing method of the present invention includes the following steps:

[0015] First, see Figure 2A As shown, a gate oxide layer 22 is formed on a substrate 20 by thermal oxidation; then on the gate oxide layer 22, a polysilicon layer 24 is deposited by chemical vapor deposition (CVD), and the polysilicon is etched away by lithography...

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Abstract

In the method, a sidewall polymer is formed at two sides of grid and to use the grid and sidewall polymer as shielding to carry on a shallow ion implanting step after a gate oxide layer and polysilicon grid are formed on a substrate surface. A shallow in doping region can be formed in the substrate outside of the sidewall polymer by utilizing the width of this sidewall polymer so the shallow ion doping region can be diffused horizontally to the substrate under the sidewall polymer to form lightly doped drain structure in the following heat preparation process.

Description

【Technical field】 [0001] The present invention relates to a method for manufacturing a semiconductor component, in particular to a method for forming a lightly doped drain (LDD) using a sidewall polymer gate structure to accurately control channel length. 【Background technique】 [0002] When the size of the component is reduced, the channel length is also relatively reduced, but the problem caused by the shortened channel length will occur. This phenomenon is called the short channel effect (short channel effect). For conventional methods to solve the hot electron effect caused by short channels, please refer to Figure 1A As shown, a gate oxide layer 12 and a polysilicon gate 14 are formed on a substrate 10, and then using the polysilicon gate 14 as a shield, shallow ion implantation is performed on the substrate 10 to form a shallow ion doped region 16, This is used as a lightly doped drain (LDD). [0003] Then form a gate spacer (spacer) 18 on the substrate 10 on both s...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/336
Inventor 蔡孟锦金平中
Owner GRACE SEMICON MFG CORP
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