Delay locking loop having acceleration mode and controlled by register

Abstract

The present invention provides for a register controlled delay locked loop having an acceleration mode for improving accuracy to be correspondent to an increase of the operation speed of a memory device. For this object, in the present intention, the register controlled delay locked loop includes a delay line, a delay model, a delay means, a first and a second phase comparators, a mode decision means, a shift register control means, and a shift register.

Description

technical field [0001] The present invention relates to a semiconductor circuit technology, and more particularly, to a register-controlled delay-locked loop (DLL) with a boost mode. Background technique [0002] In general, a clock signal of a system or a circuit is used as a reference quantity for synchronously performing timing and ensuring error-free high-speed operation. When an external clock signal of an external circuit is used in an internal circuit, a clock signal skew is generated from the internal circuit due to a timing gap between the external clock signal and the internal clock signal. A delay locked loop (hereinafter referred to as DLL) compensates clock signal skew so that the phase of the internal clock signal is equal to the phase of the external clock signal. [0003] In addition, DLLs are widely used in synchronous semiconductors including Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) due to their advantage of being less suscepti...

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Problems solved by technology

[0022] However, in the prior art, there is such a problem that not only the input clock signal rclk without delay is provided to the input clock signal of the first phase comparator 40 and the second phase comparator 44, but also the input clock signal rclk without delay is divided. With a reference clock signal ref of 1 / M

[0023] Although, in this example, it is easy to control the semiconductor memory device and reduce current consumption by using a divided clock signal such as the reference clock signal ref, various necessary timing specifications are required as the execution speed of the memory device increases. , which reduces the accuracy of the execution and becomes more complex

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