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Frequency synthesizer of using all-digit frequency detector and analogue phase detector

A frequency synthesizer and phase detector technology, applied in the direction of automatic power control, circuits that oscillate independently of each other, electrical components, etc., and can solve the problem of high jitter components of spurious frequencies

Inactive Publication Date: 2004-10-27
SEIKO EPSON CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Although a corollary of this trend is the availability of complex digital functions in the smallest area possible, integrating complex high-speed digital functions near low-headroom, high-gain analog clock components is known to result in spurious frequencies and higher jitter content

Method used

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  • Frequency synthesizer of using all-digit frequency detector and analogue phase detector
  • Frequency synthesizer of using all-digit frequency detector and analogue phase detector
  • Frequency synthesizer of using all-digit frequency detector and analogue phase detector

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Embodiment Construction

[0022] Preferred embodiments of the present invention are described below with reference to the accompanying drawings.

[0023] refer to figure 1 , the frequency synthesizer 10 or clock synthesizer according to the present invention comprises a variable oscillator 11, wherein said oscillator is preferably a voltage controlled oscillator (VCO), which has a first control input 11a and a second control input Input 11b. VCO 11 produces an oscillator output signal whose frequency depends on its first and second control inputs 11a and 11b.

[0024] The frequency synthesizer 10 also includes an analog phase detector 13 and a digital frequency difference detector (FDD) 15 . Preferably, the analog phase detector 13, also sometimes referred to as a phase frequency detector PFD, includes a charge pump not separately shown. The analog phase detector 13 has first and second phase detection inputs 13a and 13b and is operable to generate a first control signal representative of the The p...

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PUM

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Abstract

A frequency synthesizer suitable for integration in a low voltage digital CMOS process controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls the center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop, thus eliminating any static frequency error. In effect, the analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made much smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This gross parametric difference is used in the design of the VCO to allow two separate control inputs, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.

Description

technical field [0001] The present invention relates generally to the field of integrated frequency synthesizers and oscillators. In particular, the present invention is in the field of implementing variable voltage oscillators using low voltage digital CMOS processes. Background technique [0002] In modern communication systems, high-speed phase-locked loops are used for a variety of purposes, including frequency synthesis operations such as clock generation, data recovery, and retiming. This frequency synthesizer is usually an analog circuit, but in order to reduce costs, the industry tends to use a low-voltage digital CMOS process to implement this circuit. [0003] Frequency synthesizers are usually voltage controlled, so when implementing a frequency synthesizer in a low-voltage digital CMOS process, you encounter signal headroom and scalability issues. Despite these issues, the use of advanced sub-micron digital CMOS processes for implementing analog clock generatio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/187H03D13/00H03L7/087H03L7/113
CPCH03D13/003
Inventor D·梅策尔G·布伦
Owner SEIKO EPSON CORP
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