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Semiconductor structure with partial etching grid and making method thereof

A technology of local etching and gate structure, which is applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, electrical components, etc., and can solve problems affecting the pass rate and loss of semiconductor components

Inactive Publication Date: 2004-11-03
PROMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the dielectric layer (such as borophosphosilicate glass) filled between the gates, if the filling capability (gap-fill) is not good enough to cause voids (void), it will cause subsequent filling of conductive materials in the self-aligned contact (SAC) ) will cause a short circuit between the bit line contact and another adjacent bit line contact (CB to CB short), which will cause electrical loss of the semiconductor element and affect the yield of production

Method used

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  • Semiconductor structure with partial etching grid and making method thereof
  • Semiconductor structure with partial etching grid and making method thereof
  • Semiconductor structure with partial etching grid and making method thereof

Examples

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no. 1 example

[0033] The method for forming a gate structure with partial etching in the present invention, and the first embodiment of applying the gate structure with partial etching to a self-aligned contact (SAC) process will cooperate Figure 1 to Figure 7 Make a detailed description as follows.

[0034] First please refer to figure 1, providing a semiconductor substrate, such as a silicon substrate 10 , having at least two adjacent gate structures G on its surface. These gate structures G include a gate dielectric layer 12, a polysilicon layer 14, a metal silicide layer 16, and an upper cap layer 18 stacked in sequence on a silicon substrate 10, and a liner layer (liner) 20 is grown on On the surface of the silicon substrate 10 and on the side walls of the polysilicon layer 14 and the metal silicide layer 16 in the gate structure G. The above-mentioned gate dielectric layer 12, polysilicon layer 14, metal silicide layer 16, upper cover layer 18 and liner layer 20 are preferably mad...

no. 2 example

[0048] The method for forming a gate structure with partial etching in the present invention, and another embodiment of applying the gate structure with partial etching to a self-aligned contact (SAC) process will cooperate with Figure 8 to Figure 16 Make a detailed description as follows.

[0049] First please refer to Figure 8 , providing a semiconductor substrate, such as a silicon substrate 10 , having at least two adjacent gate structures G on its surface. The gate structures G are composed of a gate dielectric layer 12, a polysilicon layer 14, a metal silicide layer 16, and an upper cap layer 18 stacked in sequence on a silicon substrate 10, and a liner layer (liner) 20 grows On the surface of the silicon substrate 10 and on the side walls of the polysilicon layer 14 and the metal silicide layer 16 in the gate structure G. The above-mentioned gate dielectric layer 12, polysilicon layer 14, metal silicide layer 16, upper cover layer 18 and liner layer 20 are preferabl...

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Abstract

This invention relates to a semiconductor structure with partial etched grid and its manufacturing method including: providing a substrate with at least two adjacent grid structures composed of a grid dielectric layer, a conduction layer and a cover formed on the substrate and each side of which is covered by a lining layer to form a protection and a mask layer on the grid. One opening is defined in the mask and part of said protection layer in the opening is etched to expose part of the lining layer on a single side edge of the grid in the opening, part of the above mentioned exposed lining layer is etched and removed and to selectively remove the grid conduction layer adjacent to the lining, the mask and protection layers are removed and to form a spacer to cover each sidewall of the grid so as to form a grid structure with partial etch of multiple single side edges.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor element, in particular to a semiconductor gate structure with a partially etched gate and a manufacturing method thereof. Background technique [0002] In general, a Metal Oxide Semiconductor (MOS) device consists of a metal layer, an oxide layer and a semiconductor substrate. Due to poor adhesion between metal and oxide, polysilicon is often used instead of metal to form the conductive layer of the gate structure in the MOS device. However, the disadvantage of polysilicon is that its resistance is higher than that of metal. Although the resistance can be reduced by impurity doping, the resulting conductivity cannot be used as a good conductive layer. One of the common solutions is to add a metal silicide layer such as common tungsten silicon (WSi) on the polysilicon layer to improve the conductivity of the gate structure. In addition, the above-mentioned gate structure also includes ...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/336H01L29/78
Inventor 李岳川董明圣
Owner PROMOS TECH INC