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Manufacturing method of flash memory

A manufacturing method and flash memory technology, applied in the field of flash memory manufacturing, can solve problems such as area reduction, and achieve the effect of increasing the overlapping area and improving the coupling rate

Inactive Publication Date: 2005-01-26
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Increasing the overlapping area between the floating gate and the control gate helps to increase the gate coupling ratio. However, with the continuous pursuit of high integration in integrated circuits, the area occupied by each memory cell of the flash memory device must be reduced.

Method used

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  • Manufacturing method of flash memory
  • Manufacturing method of flash memory
  • Manufacturing method of flash memory

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Embodiment Construction

[0030] In order to make the above and other purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, as follows:

[0031] Figure 1A to Figure 1L A top view showing the manufacturing process of a flash memory according to the preferred embodiment of the present invention. Figure 2A to Figure 2L for Figure 1A to Figure 1L The cross-sectional view of the I-I' line. First please also refer to Figure 1A and Figure 2A , providing a substrate 100, such as a silicon substrate. Then, a tunnel dielectric layer 102 , a conductive layer 104 and a mask layer 106 are sequentially formed on the substrate 100 . The material of the tunneling dielectric layer 102 is, for example, silicon oxide, and its thickness is, for example, about 50 angstroms to 100 angstroms.

[0032] The tunneling dielectric layer 102 is formed by thermal oxidation or low pressure chemical vapor d...

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Abstract

The invention is a flash memory manufacturing method, firstly on a substrate, forming a grid structure composed of patternized tunneled dielectric layer, conductor layer and mask layer and forming a buried drain in the substrate, then forming an insulating layer around the grid structure, where the surface of the insulating layer is lower than the top surface of the patternized conductor layer in the grid structure, successively removing the patternized mask layer, then forming the other patternized conductor layer extending to the surface of the insualting layer on the patternized conductor layer, where the two conductor layers compose a floating grid, successively removing matierla layer, forming a grid-grid dielectric layer on the surface exposed by the floating grid, and then forming control grid on the grid-grid dielectric layer.

Description

technical field [0001] The present invention relates to a manufacturing method of flash memory, in particular to a manufacturing method of flash memory which increases the overlapping area between the floating gate and the control gate. Background technique [0002] Flash memory devices have become a memory device widely used in personal computers and electronic equipment due to their superior data storage characteristics. [0003] A typical flash memory device is generally designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a polysilicon floating gate (Floating Gate) for storing charges, silicon monoxide / nitrogen A dielectric layer of silicon oxide / silicon oxide (Oxide-Nitride-Oxide, ONO) structure, and a polysilicon control gate (Control Gate) for controlling data access. [0004] In the operation of flash memory, the larger the gate-coupling ratio (Gate-Coupling Ratio, GCR) between the floating gate and the control gate, the lower...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H10B20/00H10B99/00
Inventor 陈光钊吕瑞霖杨令武
Owner MACRONIX INT CO LTD
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