Method for testing a circuit which is under test, and circuit configuration for carrying out the method

Abstract

A circuit configuration for testing a circuit that is under test using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve actual data that are output by the circuit under test on the basis of supplied test data are compared with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.

Description

technical field [0001] The present invention generally relates to a method for testing a circuit unit, in particular to a method for testing a circuit unit under test having at least one memory cell array and at least one addressing and control unit, and a method utilizing The terminal unit provided on the circuit structure realizes the circuit structure of the method. Background technique [0002] There is an increasing need to implement a wide range of testing processes in parallel at low testing costs. The circuit unit to be tested is primarily a memory chip with increased complexity. In this case, the test cost is mainly determined by the test time and obtained according to the number of circuit units under test that can be tested within a predetermined time. [0003] The number of testable circuit units per unit time is also called throughput rate. In order to reduce the cost of each circuit unit under test as a whole, it has been proposed to reduce the test time or ...

AI Technical Summary

Problems solved by technology

[0011] Therefore, the main disadvantage of the conventional circuit structure for testing the circuit unit under test is that, in addition to the addressing and control terminal unit 108 for enabling the memory cell array 101 in the circuit unit 100 under test, only Terminal unit 204 is provided for testing purposes

This extra connection pin untimely increases the cost of the circuit unit under test and the overall cost of testing

Furthermore, the conventional circuit architecture does not allow any significant degree of parallel testing

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