D trigger with resetting and/or setting functions, and based on conditional preliminary filling structure

Abstract

Characters of the invention are as following: besides structure of sensitive amplifier is adopted in latch in first stage, pull-up and pull-down are carried out for two complemental output ends by using two pieces of P tubes and two pieces of N tubes at power source end and complemental output ends respectively. Control signals pulled-up and pulled-down are set and reset signals. Two pieces of phase latches in single clock with identical circuit parameter are adopted in latch in second stage. Potential retention unit structured from two inverters connected at headers is added between output ends of two pieces of phase latches. Comparing prior art, the invention saves energy 20% under same testing condition. Moreover, the invention possesses features of simple structure, small area of circuit, good characteristics of circuit time delay, setup time and metastable state time.

Description

technical field [0001] The technical field of the direct application of the D flip-flop based on the conditional precharge structure with the reset setting function is the low power consumption flip-flop circuit design with the reset setting function based on the conditional precharge structure. The proposed circuit is a kind of low-power CMOS flip-flop circuit unit which is suitable for low-swing clock signal network technology and needs to reset the set terminal. Background technique [0002] With the advancement of CMOS integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the energy consumed by the clock network accounts for a high proportion of the total energy consumption of th...

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Problems solved by technology

However, the problem with the SAFF_CP circuit is that since the output latch circuit adopts a cross-coupled NAND2 (NAND2: two-input NAND gate) structure, the delay of the rising edge and falling edge of the output of the flip-flop circuit will be extremely different. Symmetry, which poses potential problems for the use of circuit cells

This kind of structural circuit is relatively complicated, and only the first-level reset method is given, without considering the priority design when the reset bits appear at the same time, lack of design for different second-level reset bits, and cannot be simply applied image 3 The SAFF_CP flip-flop structure shown

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