Operation scheme for spectrum shift in charge trapping non-volatile memory

Abstract

A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tending to the induce balanced charge tunneling between the gate and the charge trapping structure and between the charge trapping structure in the channel. A second procedure (typically program) is used to establish a high threshold state in the memory cell, including a third bias arrangement that causes an increase in negative charge in the charge trapping structure.

Description

technical field [0001] The present invention relates to an electrically programmable and erasable nonvolatile memory, and more particularly to a charge trapping memory with a bias arrangement, in addition to boost and In addition to the operation of lowering the starting voltage, it can also be used to correct the charge in the memory. Background technique [0002] EEPROM technology is based on charge storage structures, such as EEPROM and flash memory, which are commonly used in various modern applications. Many memory cell structures are used in EEPROM and flash memory. Due to the simplicity and scalability of semiconductor manufacturing, interest in memory cell structures with charge-trapping dielectric layers has increased as the size of integrated circuits has shrunk. The memory cell structure with the charge trapping dielectric layer includes, for example, industrial names such as Nitride Read Only Memory (NROM), Silicon Oxide Nitride Oxide Silicon (SONOS) and PHINES...

AI Technical Summary

Problems solved by technology

However, electrons with shallow energy levels have an important problem that the charge is difficult to preserve

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