Test switching circuit for a high speed data interface

Abstract

Test switching circuit for a high speed data interface ( 1 ) of an integrated circuit comprising switching transistors (T 1 -T 6 ) which switch in a test mode a termination resistor output stage ( 15 ) of a data transmission signal path ( 17 ) to a termination resistor input stage ( 18 ) of a data reception signal path ( 25 ) to form an internal feedback test loop within said integrated circuit.

Description

technical field [0001] The present invention relates to a test switching circuit for a high speed data interface of an integrated circuit. Background technique [0002] High speed communication circuits transmitting data at rates in the 10Gbps range require closed feedback loops for testing purposes. figure 1 Represents a high-speed communication integrated circuit with a core for data processing and several high-speed interfaces. The high-speed data interface or serializer / deserializer (SERDES) module operates at a rate of up to 10Gbps. Each high-speed data interface (SERDES) is connected to a data transmission line (TX) and a data reception line (RX). The high-speed data interface transmits data via the data transmission line (TX) and receives data via the data reception line (RX). [0003] figure 2 Denotes a conventional high-speed data interface according to the prior art. The high-speed data interface includes a transmitter and a receiver. Such as figure 2 The ...

AI Technical Summary

Problems solved by technology

The provision of an external loop has the following disadvantages: due to the insertion of multiple system tests, it increases the cost of testing; or the insertion of a single test loop causes the RF switch to be used, thus increasing the complexity of the load board.

[0015] like Figure 3 to Figure 5 The internal test circuit used to create an internal test loop in the prior art shown has several severe disadvantages

[0016] The first disadvantage is that if image 3 ,Figure 4, Figure 5 The arrangement shown makes it impossible to test either a final output stage, such as the differential amplifier stage D-AMP-C shown in Figure 4, and an input driver stage at the input, such as the Figure 5 The real function of the differential amplifier stage D-AMP-D shown in the figure

When a manufacturing error occurs in the differential amplifier stage D-AMP-C or in the differential amplifier stage D-AMP-D, it will not be detected by the internal test signal analyzer

Moreover, errors in the manufacture of the programmable termination resistor level cannot be detected by the high-speed data interface circuit according to the prior art.

[0017] Another disadvantage of the conventional circuit is that by means of the critical output N of the first differential amplifier stage D-AMP-A, Provide an additional differential amplifier stage D-AMP-B, the parasitic capacitance on this node will increase (transistor T B , for transistor T A , form an additional load), the normal operation mode of the data transmission path from the differential amplifier stage D-AMP-C to the output data pin will eventually cause a redesign of the normal mode circuit, representing a power consumption P compared to increased from the original design to maintain the required bandwidth

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