Non-volatile memory device having improved erase efficiency and method of manufacturing the same

Abstract

The invention discloses a nonvolatile memory with improved erasing efficiency and a preparation method thereof. The method includes: forming a stacked structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer, and a gate on a semiconductor substrate; and post-processing the gate using oxygen or CF4 plasma or ion implantation to increase the formation of The work function of the gate material. According to the present invention, since the work function of the metal layer forming the gate can also be increased, electron backtunneling during an erase operation can be suppressed.

Description

technical field [0001] The invention relates to a semiconductor device, more specifically, to a nonvolatile memory with improved erasing efficiency and a preparation method thereof. Background technique [0002] As the name implies, nonvolatile memory has the property of retaining data even after power is turned off. These nonvolatile memories have a charge trapping layer formed between a gate of a transistor and a channel through which charges are trapped, thereby realizing a threshold voltage difference of the channel. Threshold voltage V th The gate voltage V g It also changes accordingly. Therefore, the threshold voltage V is changed by trapping or storing charges in the charge-trapping layer th This idea, to realize the operation of the non-volatile memory. [0003] In a typical flash memory device, a polysilicon floating gate using a metal layer or a metalloid layer has been used as a charge trapping layer. Furthermore, in silicon-oxide-nitride-oxide-silicon (SON...

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Problems solved by technology

However, when a voltage for an erase operation is applied to the gate, it may cause back-tunneling, where electrons introduced between the gate and the charge-trapping layer move from the gate to the charge-trapping layer

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