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Method for protecting silicon oxide layer in low-voltage field by CMOS high-voltage process

A technology of silicon oxide layer and low-voltage area, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of affecting the thickness of the field silicon oxide layer, loss of insulation isolation, etc., and achieve the effect of low cost and simple process

Inactive Publication Date: 2006-11-01
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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Problems solved by technology

If these two or three thickness gate silicon oxide layers are fabricated on the same chip, the main process problem arising from this is that when embedding a thick gate silicon oxide layer process, it will seriously affect the low-voltage circuit (core logic circuit) area. The thickness of the silicon oxide layer in the field makes it lose the effect of insulation isolation

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  • Method for protecting silicon oxide layer in low-voltage field by CMOS high-voltage process
  • Method for protecting silicon oxide layer in low-voltage field by CMOS high-voltage process
  • Method for protecting silicon oxide layer in low-voltage field by CMOS high-voltage process

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Embodiment Construction

[0031] Now in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail:

[0032] First, if figure 1 as shown ( figure 1 is a schematic diagram of the formation of field silicon oxide), and the required field silicon oxide layer is formed on the silicon substrate. The process of forming the field silicon oxide layer can be a LOCOS (local oxidation) process or an STI (shallow trench isolation) process. .

[0033] Secondly, if figure 2 as shown ( figure 2 It is a schematic diagram of growing a bottom silicon oxide layer, a silicon nitride layer and a top silicon oxide layer as a shielding layer), using a thermal oxidation method to grow a bottom silicon oxide layer on the substrate silicon and a field silicon oxide layer, and using chemical vapor deposition (CVD) A silicon nitride layer is grown on the silicon oxide layer, and a top silicon oxide layer (HTO) is grown on the silicon nitride layer using chemical va...

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Abstract

The method comprises: a sandwich layer containing silicon nitride formed by bottom silicon oxide layer, silicon nitride layer and upper silicon oxide layer is used to replace the thermal oxide layer and to be taken as the Pad-oxide of high voltage well ion injection; the silicon nitride layer in the sandwich layer is used to make patterning in order to let it protect the active region and field silicon oxide in low voltage circuit (core logical circuit) from the high voltage fabrication process such that the adding of mask is avoided.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit technology, and in particular relates to a method for protecting a silicon oxide layer in a low-voltage region in a CMOS high-voltage technology. Background technique [0002] With the continuous improvement of CMOS circuit integration, a variety of circuits and devices working at different voltages are often integrated on the same chip. The more common ones are low voltage (1.0V to 3.3V), medium voltage (2.5V to 5V ) and high voltage (12V to 40V) circuits are integrated in the same chip LCDDriver / Controller and various chips with embedded memory, etc. For this reason, it is necessary to embed medium and high voltage process modules in the standard CMOS process flow. Its basic process flow is in the standard CMOS device (core logic circuit) manufacturing process flow, the ion implantation process and the thick gate silicon oxide layer process are embedded in the corresponding steps of h...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L21/265H01L21/3105H01L21/3115
Inventor 陈寿面
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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