Semiconductor device and process for fabricating the same

Abstract

A thin stacked semiconductor device suitable for high speed operation. A plurality of specified circuits are formed on one surface of a semiconductor substrate while being arranged, and wiring and insulating layers being connected electrically with the circuits are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, forward end of the through-type electrode is projected by etching one surface of the semiconductor substrate, a second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, bump electrodes are formed on both electrodes and then the semiconductor substrate is divided to form a semiconductor device. A plurality of semiconductor devices thus obtained are stacked and secured at the bump electrodes thus manufacturing a stacked semiconductor device.

Description

technical field [0001] The present invention relates to a thinner and faster-operating semiconductor device and its manufacturing method, and more particularly to an extremely efficient manufacturing technique for sequentially stacking a plurality of semiconductor devices to manufacture a stacked semiconductor device. Background technique [0002] Along with the development of various electronic devices in terms of multi-function and miniaturization, the semiconductor device embedded in the electronic device has gradually evolved into a structure in which many circuit elements are built in a small volume. As a method for increasing the integration density of semiconductor devices (integrated circuit devices), three-dimensional stacked semiconductor devices are known. [0003] For example, a structure for achieving high integration by stacking and fixing LSI chips having through-electrodes penetrating multiple stages on an interposer has been proposed...

AI Technical Summary

Problems solved by technology

However, as the number of welding lines increases, the number of processes also becomes longer

In addition, the connection path becomes longer and the impedance increases due to the bonding wire, which may lead to deterioration of characteristics (high-speed operation)

Furthermore, there is a problem with the processing of the thinned bare chip (Bare Chip), and there are limitations in the overall thinning

[0013] (3) In order to improve the yield of finished products, the final test must be carried out with bare chips before installation (stacking); : known good chip) the cost of the final test is very high

[0014] (4) When stacking multiple positions on one chip, the maximum of 2 layers is already the limit, and even so, the connection path will become longer, which will easily affect the characteristics

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