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Semiconductor device and semiconductor device production method

A technology for semiconductors and manufacturing methods, applied in the field of semiconductor devices, can solve the problems of difficulty in ensuring the flatness of connecting electrodes, increased connection load, poor contact, etc., and achieves increased process design freedom, increased flatness and improved reliability Effect

Inactive Publication Date: 2007-04-11
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, a part of the connection terminals 2 of the semiconductor element 1 is separated from the connection electrodes of the substrate 5, and there is a high possibility of poor contact.
[0009] In this way, as the number of connecting parts increases, the flatness of the substrate is required. However, the above-mentioned warping of the substrate makes it difficult to secure the flatness required for electrical connection in the connection electrodes.
Moreover, the more the number of connection parts increases, the more the connection load for connecting the connection terminals of the semiconductor element to the connection electrodes of the substrate increases.

Method used

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  • Semiconductor device and semiconductor device production method
  • Semiconductor device and semiconductor device production method
  • Semiconductor device and semiconductor device production method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0052] FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1 of the present invention. As shown in Figure 1, the substrate 5 does not form a solder resist layer on the two main surfaces of the front and back, but the connection electrode 4 is arranged on the position sunken from the main surface on one main surface, and the connection electrode 4 is arranged on the sunken position on the other main surface. Position the external electrode 7 . Then, via 6 provided inside substrate 5 electrically connects connection electrode 4 and external electrode 7 , and external terminal 8 is formed on external electrode 7 .

[0053] The height from the surface of the connection electrode 4 to one main surface of the substrate 5 and the height from the surface of the external electrode 7 to the other main surface of the substrate 5 are equal to the thickness of the solder resist layer when the solder resist layer is formed, specifically ...

Embodiment 2

[0068] 2 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2 of the present invention. In FIG. 2, the surface of the connection electrode 4 arranged on one main surface of the substrate 5 is at the same height as the main surface. The external electrode 7 arranged on the other main surface of the substrate 5 is arranged at a position sunken from the main surface of the substrate 5 .

[0069] The height from the surface of the external electrode 7 to the main surface of the substrate 5 is equal to the thickness of the solder resist layer when the solder resist layer is formed, and specifically, it is preferably formed to be equal to or greater than 10 micrometers. The other composition is the same as the above-mentioned embodiment 1, and detailed description is omitted.

[0070] In this composition, by providing the external electrode 7 at the position sunken from the main surface of the substrate 5, even if no solder resist laye...

Embodiment 3

[0074] 3 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2 of the present invention. In FIG. 3 , connection electrode 4 arranged on one main surface of substrate 5 is arranged at a position sunken from the main surface of substrate 5 . The height from the surface of the connection electrode 4 to the main surface of the substrate 5 is equal to the thickness of the solder resist layer when the solder resist layer is formed, specifically, it is preferably formed to be greater than or equal to 10 microns.

[0075] The external electrodes 7 arranged on the other main surface of the substrate 5 are exposed in openings where the solder resist layer 10 is formed on the other main surface of the substrate 5 . The surface of external electrode 7 is at the same height as the main surface of substrate 5 . Other compositions are the same as in Example 1, and detailed descriptions are omitted.

[0076] In the semiconductor device of the ab...

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PUM

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Abstract

The present invention provides a semiconductor device in which the warp of a board is suppressed without the need for provision of a solder resist on opposite surfaces of the board and semiconductor element connection characteristics are improved by reducing stress exerted on a connection portion, and increases flexibility in assembly process.

Description

field of invention [0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The technology relates to a semiconductor device that protects the integrated circuit portion of an LSI chip, ensures stable electrical connection between an external device and the LSI chip, and can be mounted at a high density. A semiconductor device of a semiconductor element. Background technique [0002] In recent years, the miniaturization of industrial electronic equipment such as information and communication equipment, business electronic equipment, household electronic equipment, measuring equipment, assembly robots, medical electronic equipment, and electronic toys has been carried out, and there is a strong demand for miniaturization of the mounting area of ​​semiconductor devices. . [0003] As a measure to respond to these demands, a BGA (Ball Grid Array) or the like is used. On the other hand, as the density of semiconducto...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/12H01L21/60
CPCH01L2224/81801H05K1/113H01L2224/32225H01L2224/13144H01L2224/16H01L2924/0105H01L2924/01047H01L2224/16225H01L2924/3511H01L2924/01078H01L2924/01006H05K2201/09472H01L2924/01079H01L2224/8101H01L2924/14H01L2924/15311H01L2224/83102H01L2224/16237H01L2224/83192H01L2924/01082H01L2224/73204H01L2224/92125H01L2224/13147H05K2201/10674H01L2924/014H01L2224/81203H01L2924/01029H01L23/49816H01L2224/81024H01L2924/01033H05K2201/096H01L24/81H01L2224/16235H01L2924/181H01L2924/00
Inventor 大隅贵寿
Owner PANASONIC CORP