Semiconductor device and integrated circuit device

Abstract

A semiconductor structure includes a first dielectric layer having a k value of less than about 2.7, a second dielectric layer over the first dielectric layer, a via in the first dielectric layer, a conductive line in the second dielectric layer, wherein the conductive line extends from a top surface of the second dielectric layer into the second dielectric layer and electrically coupled to the via, a third dielectric layer on the second dielectric layer, and a fourth dielectric layer between the second dielectric layer and the conductive line. The second dielectric layer is preferably a porous material and has an ultra low k value. The k value of the second dielectric layer is lower than the k values of the first, the third and the fourth dielectric layers.

Description

technical field [0001] The present invention relates to the manufacturing process of semiconductor integrated circuits, in particular to the damascene process utilizing the dielectric layer of ultra-low dielectric constant. Background technique [0002] Integrated circuit technology has opened a new era in the semiconductor industry due to the advantages of reducing the size of components to increase the density of components. Component density is limited by the capabilities of the lithography process, and shrinking component dimensions creates new constraints. For example, for any two adjacent conductors, the closer the distance between the conductors is, the larger the capacitance (which is a function of the distance between the two conductors and the dielectric constant (k) of the material of the insulating layer therebetween) is greater. An increase in capacitance results in increased capacitive coupling and power dissipation between the two conductors, thus slowing dow...

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Problems solved by technology

[0006] The disadvantage of inherently weak mechanical hardness limits the use of porous dielectric layer materials

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